OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:269-272 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 269 - 272

--------------------------------------------------------------------------------

269: #pragma omp parallel for simd

270:       for (int j = (x_min - depth + 1); j < (x_max + depth + 2); j++) {

271:         for (int k = 0; k < depth; ++k) {

272:           field.viscosity(j, y_max + 2 + k) = field.viscosity(j, y_max + 1 - k);

0x430620 STP	X29, X30, [SP, #976]!

0x430624 ADD	X29, SP, #0

0x430628 STP	X19, X20, [SP, #16]

0x43062c LDR	W19, [X0, #8]

0x430630 STP	X21, X22, [SP, #32]

0x430634 ORR	X22, XZR, X0

0x430638 LDR	W20, [X0, #20]

0x43063c SUB	W0, W19, W20

0x430640 ADD	W19, W0, #1

0x430644 BL	403530

0x430648 ORR	W21, WZR, W0

0x43064c BL	4033c0

0x430650 LDR	W2, [X22, #12]

0x430654 ORR	W1, WZR, W0

0x430658 ADD	W3, W20, W2

0x43065c ADD	W4, W3, #2

0x430660 SUB	W5, W4, W19

0x430664 SDIV	W6, W5, W21

0x430668 MSUB	W7, W6, W21, W5

0x43066c CMP	W0, W7

0x430670 B.LT	430848

(483) 0x430674 MADD	W8, W6, W1, W7

(483) 0x430678 ADD	W9, W6, W8

(483) 0x43067c CMP	W8, W9

(483) 0x430680 B.GE	430838

(483) 0x430684 ADD	W10, W19, W8

(483) 0x430688 LDR	W11, [X22, #16]

(483) 0x43068c ADD	W19, W19, W9

(483) 0x430690 LDR	X12, [X22]

(483) 0x430694 CMP	W20, #0

(483) 0x430698 B.LE	430838

(483) 0x43069c ADD	W13, W11, #1

(483) 0x4306a0 SBFM	X4, X10, #0, #31

(483) 0x4306a4 LDR	X15, [X12, #120]

(483) 0x4306a8 SBFM	X14, X13, #0, #31

(483) 0x4306ac MOVZ	W30, #0

(483) 0x4306b0 LDR	X18, [X12, #136]

(483) 0x4306b4 MADD	X21, X14, X15, XZR

(483) 0x4306b8 SUB	X0, XZR, X15,LSL #3

(483) 0x4306bc ADD	X22, X15, X21

  (485) 0x4306c0 ADD	X16, X4, X21

  (485) 0x4306c4 ADD	X17, X4, X22

  (485) 0x4306c8 ANDS	W5, W20, #128

  (485) 0x4306cc ADD	X1, X18, X16,LSL #3

  (485) 0x4306d0 MOVZ	W3, #0

  (485) 0x4306d4 ADD	X2, X18, X17,LSL #3

  (485) 0x4306d8 B.EQ	4307a0

  (485) 0x4306dc CMP	W5, #1

  (485) 0x4306e0 B.EQ	430784

  (485) 0x4306e4 CMP	W5, #2

  (485) 0x4306e8 B.EQ	430770

  (485) 0x4306ec CMP	W5, #3

  (485) 0x4306f0 B.EQ	43075c

  (485) 0x4306f4 CMP	W5, #4

  (485) 0x4306f8 B.EQ	430748

  (485) 0x4306fc CMP	W5, #5

  (485) 0x430700 B.EQ	430734

  (485) 0x430704 CMP	W5, #6

  (485) 0x430708 B.EQ	430720

  (485) 0x43070c LDR	D0, [X18, X16,LSL #3]

  (485) 0x430710 ADD	X1, X1, X0

  (485) 0x430714 SUB	X2, X2, X0

  (485) 0x430718 MOVZ	W3, #1

  (485) 0x43071c STR	D0, [X18, X17,LSL #3]

  (485) 0x430720 LDR	D1, [X1]

  (485) 0x430724 ADD	W3, W3, #1

  (485) 0x430728 ADD	X1, X1, X0

  (485) 0x43072c STR	D1, [X2]

  (485) 0x430730 SUB	X2, X2, X0

  (485) 0x430734 LDR	D2, [X1]

  (485) 0x430738 ADD	W3, W3, #1

  (485) 0x43073c ADD	X1, X1, X0

  (485) 0x430740 STR	D2, [X2]

  (485) 0x430744 SUB	X2, X2, X0

  (485) 0x430748 LDR	D3, [X1]

  (485) 0x43074c ADD	W3, W3, #1

  (485) 0x430750 ADD	X1, X1, X0

  (485) 0x430754 STR	D3, [X2]

  (485) 0x430758 SUB	X2, X2, X0

  (485) 0x43075c LDR	D4, [X1]

  (485) 0x430760 ADD	W3, W3, #1

  (485) 0x430764 ADD	X1, X1, X0

  (485) 0x430768 STR	D4, [X2]

  (485) 0x43076c SUB	X2, X2, X0

  (485) 0x430770 LDR	D5, [X1]

  (485) 0x430774 ADD	W3, W3, #1

  (485) 0x430778 ADD	X1, X1, X0

  (485) 0x43077c STR	D5, [X2]

  (485) 0x430780 SUB	X2, X2, X0

  (485) 0x430784 LDR	D6, [X1]

  (485) 0x430788 ADD	W3, W3, #1

  (485) 0x43078c ADD	X1, X1, X0

  (485) 0x430790 STR	D6, [X2]

  (485) 0x430794 SUB	X2, X2, X0

  (485) 0x430798 CMP	W20, W3

  (485) 0x43079c B.EQ	430828

    (484) 0x4307a0 LDR	D7, [X1]

    (484) 0x4307a4 SUB	X17, X2, X0

    (484) 0x4307a8 ADD	X16, X1, X0

    (484) 0x4307ac SUB	X15, X17, X0

    (484) 0x4307b0 ADD	X14, X16, X0

    (484) 0x4307b4 SUB	X13, X15, X0

    (484) 0x4307b8 ADD	X12, X14, X0

    (484) 0x4307bc SUB	X11, X13, X0

    (484) 0x4307c0 ADD	X10, X12, X0

    (484) 0x4307c4 SUB	X9, X11, X0

    (484) 0x4307c8 ADD	X8, X10, X0

    (484) 0x4307cc SUB	X7, X9, X0

    (484) 0x4307d0 ADD	X6, X8, X0

    (484) 0x4307d4 STR	D7, [X2]

    (484) 0x4307d8 SUB	X5, X7, X0

    (484) 0x4307dc ADD	W3, W3, #8

    (484) 0x4307e0 LDR	D16, [X1, X0]

    (484) 0x4307e4 SUB	X2, X5, X0

    (484) 0x4307e8 ADD	X1, X6, X0,LSL #1

    (484) 0x4307ec STR	D16, [X17]

    (484) 0x4307f0 LDR	D17, [X16, X0]

    (484) 0x4307f4 STR	D17, [X15]

    (484) 0x4307f8 LDR	D18, [X14, X0]

    (484) 0x4307fc STR	D18, [X13]

    (484) 0x430800 LDR	D19, [X12, X0]

    (484) 0x430804 STR	D19, [X11]

    (484) 0x430808 LDR	D20, [X10, X0]

    (484) 0x43080c STR	D20, [X9]

    (484) 0x430810 LDR	D21, [X8, X0]

    (484) 0x430814 STR	D21, [X7]

    (484) 0x430818 LDR	D22, [X6, X0]

    (484) 0x43081c STR	D22, [X5]

    (484) 0x430820 CMP	W20, W3

    (484) 0x430824 B.NE	4307a0

  (485) 0x430828 ADD	X4, X4, #1

  (485) 0x43082c ADD	W3, W30, W4

  (485) 0x430830 CMP	W19, W3

  (485) 0x430834 B.GT	4306c0

(483) 0x430838 LDP	X19, X20, [SP, #16]

(483) 0x43083c LDP	X21, X22, [SP, #32]

(483) 0x430840 LDP	X29, X30, [SP], #48

(483) 0x430844 RET

(483) 0x430848 ADD	W6, W6, #1

(483) 0x43084c MOVZ	W7, #0

(483) 0x430850 B	430674

0x430854 HINT	#0

0x430858 HINT	#0

0x43085c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:269-272
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:269-272

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430620

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430848 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:269-272
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:269-272

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430620

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430848 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.21]–	0.02	0
▼Loop 483 - update_halo.cpp:269-272 - exec–	0	0
▼Loop 485 - update_halo.cpp:271-272 - exec–	0.02	0
○Loop 484 - update_halo.cpp:271-272 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code