OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:246-249 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 246 - 249

--------------------------------------------------------------------------------

246: #pragma omp parallel for simd

247:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

248:         for (int j = 0; j < depth; ++j) {

249:           field.pressure(x_max + 2 + j, k) = field.pressure(x_max + 1 - j, k);

0x4301ec STP	X29, X30, [SP, #976]!

0x4301f0 ADD	X29, SP, #0

0x4301f4 STP	X19, X20, [SP, #16]

0x4301f8 LDR	W19, [X0, #12]

0x4301fc STP	X21, X22, [SP, #32]

0x430200 ORR	X22, XZR, X0

0x430204 LDR	W20, [X0, #20]

0x430208 SUB	W0, W19, W20

0x43020c ADD	W19, W0, #1

0x430210 BL	403530

0x430214 ORR	W21, WZR, W0

0x430218 BL	4033c0

0x43021c LDR	W2, [X22, #16]

0x430220 ORR	W1, WZR, W0

0x430224 ADD	W3, W20, W2

0x430228 ADD	W4, W3, #2

0x43022c SUB	W5, W4, W19

0x430230 SDIV	W6, W5, W21

0x430234 MSUB	W7, W6, W21, W5

0x430238 CMP	W0, W7

0x43023c B.LT	4303e4

  (479) 0x430240 MADD	W8, W6, W1, W7

  (479) 0x430244 ADD	W9, W6, W8

  (479) 0x430248 CMP	W8, W9

  (479) 0x43024c B.GE	4303d4

  (479) 0x430250 ADD	W10, W19, W8

  (479) 0x430254 LDR	W13, [X22, #8]

  (479) 0x430258 ADD	W19, W19, W9

  (479) 0x43025c LDR	X11, [X22]

  (479) 0x430260 CMP	W20, #0

  (479) 0x430264 B.LE	4303d4

(477) 0x430268 ADD	W14, W13, #1

(477) 0x43026c SBFM	X5, X10, #0, #31

(477) 0x430270 LDR	X16, [X11, #96]

(477) 0x430274 SBFM	X14, X14, #0, #31

(477) 0x430278 SBFM	X13, X13, #0, #31

(477) 0x43027c MOVZ	W15, #0

(477) 0x430280 LDR	X6, [X11, #112]

(477) 0x430284 MADD	X12, X16, X5, XZR

(477) 0x430288 SUB	W17, W20, #1

(477) 0x43028c MOVZ	X0, #1

(477) 0x430290 AND	W18, W17, #128

(477) 0x430294 ADD	X30, X14, X12

(477) 0x430298 ADD	X22, X13, X12

(477) 0x43029c UBFM	X21, X22, #61, #60

(477) 0x4302a0 ADD	X4, X6, X30,LSL #3

(477) 0x4302a4 LDR	D0, [X6, X30,LSL #3]

(477) 0x4302a8 ADD	X2, X21, #16

(477) 0x4302ac ADD	X3, X6, X2

(477) 0x4302b0 SUB	X1, X4, #8

(477) 0x4302b4 STR	D0, [X6, X2]

(477) 0x4302b8 CMP	W20, #1

(477) 0x4302bc B.LE	4303c4

(477) 0x4302c0 CBZ	W18, 430354

0x4302c4 CMP	W18, #1

0x4302c8 B.EQ	430340

0x4302cc CMP	W18, #2

0x4302d0 B.EQ	430334

0x4302d4 CMP	W18, #3

0x4302d8 B.EQ	430328

0x4302dc CMP	W18, #4

0x4302e0 B.EQ	43031c

0x4302e4 CMP	W18, #5

0x4302e8 B.EQ	430310

0x4302ec CMP	W18, #6

0x4302f0 B.EQ	430304

0x4302f4 LDUR	D1, [X4, #504]

0x4302f8 SUB	X1, X1, #8

0x4302fc MOVZ	X0, #2

0x430300 STR	D1, [X3, #8]

0x430304 LDR	D2, [X1], #504

0x430308 STR	D2, [X3, X0,LSL #3]

0x43030c ADD	X0, X0, #1

0x430310 LDR	D3, [X1], #504

0x430314 STR	D3, [X3, X0,LSL #3]

0x430318 ADD	X0, X0, #1

0x43031c LDR	D4, [X1], #504

0x430320 STR	D4, [X3, X0,LSL #3]

0x430324 ADD	X0, X0, #1

0x430328 LDR	D5, [X1], #504

0x43032c STR	D5, [X3, X0,LSL #3]

0x430330 ADD	X0, X0, #1

0x430334 LDR	D6, [X1], #504

0x430338 STR	D6, [X3, X0,LSL #3]

0x43033c ADD	X0, X0, #1

0x430340 LDR	D7, [X1], #504

0x430344 STR	D7, [X3, X0,LSL #3]

0x430348 ADD	X0, X0, #1

0x43034c CMP	W20, W0

0x430350 B.LE	4303c4

  (478) 0x430354 ORR	X17, XZR, X1

  (478) 0x430358 ADD	X18, X0, #1

  (478) 0x43035c ADD	X12, X0, #2

  (478) 0x430360 ADD	X11, X0, #3

  (478) 0x430364 LDR	D16, [X17], #504

  (478) 0x430368 ADD	X10, X0, #4

  (478) 0x43036c ADD	X9, X0, #5

  (478) 0x430370 ADD	X8, X0, #6

  (478) 0x430374 ADD	X7, X0, #7

  (478) 0x430378 SUB	X1, X1, #64

  (478) 0x43037c STR	D16, [X3, X0,LSL #3]

  (478) 0x430380 ADD	X0, X0, #8

  (478) 0x430384 LDR	D17, [X1, #56]

  (478) 0x430388 STR	D17, [X3, X18,LSL #3]

  (478) 0x43038c LDUR	D18, [X17, #504]

  (478) 0x430390 STR	D18, [X3, X12,LSL #3]

  (478) 0x430394 LDR	D19, [X1, #40]

  (478) 0x430398 STR	D19, [X3, X11,LSL #3]

  (478) 0x43039c LDR	D20, [X1, #32]

  (478) 0x4303a0 STR	D20, [X3, X10,LSL #3]

  (478) 0x4303a4 LDR	D21, [X1, #24]

  (478) 0x4303a8 STR	D21, [X3, X9,LSL #3]

  (478) 0x4303ac LDR	D22, [X1, #16]

  (478) 0x4303b0 STR	D22, [X3, X8,LSL #3]

  (478) 0x4303b4 LDR	D23, [X1, #8]

  (478) 0x4303b8 STR	D23, [X3, X7,LSL #3]

  (478) 0x4303bc CMP	W20, W0

  (478) 0x4303c0 B.GT	430354

(477) 0x4303c4 ADD	X5, X5, #1

(477) 0x4303c8 ADD	W30, W15, W5

(477) 0x4303cc CMP	W19, W30

(477) 0x4303d0 B.GT	430284

  (479) 0x4303d4 LDP	X19, X20, [SP, #16]

  (479) 0x4303d8 LDP	X21, X22, [SP, #32]

  (479) 0x4303dc LDP	X29, X30, [SP], #48

  (479) 0x4303e0 RET

  (479) 0x4303e4 ADD	W6, W6, #1

  (479) 0x4303e8 MOVZ	W7, #0

  (479) 0x4303ec B	430240

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:246-249
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:246-249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 5.17 cycles (1.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 9.00 to 1.46 cycles (6.17x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50
cycles	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	7.13
Overall L1	9.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

7% of peak load performance is reached (7.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4301ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 4303e4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430340 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430334 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430328 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43031c <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430310 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430304 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D1, [X4, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D1, [X3, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDR D2, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4303c4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:246-249
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:246-249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 5.17 cycles (1.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50
cycles	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	7.13
Overall L1	9.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

7% of peak load performance is reached (7.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4301ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 4303e4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430340 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430334 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430328 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43031c <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430310 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 430304 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D1, [X4, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D1, [X3, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDR D2, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4303c4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.19]–	0.02	0
▼Loop 477 - update_halo.cpp:246-249 - exec–	0.02	0
○Loop 479 - update_halo.cpp:246-249 - exec	0	0
○Loop 478 - update_halo.cpp:248-249 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code