OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:236-239 [...]	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 236 - 239

--------------------------------------------------------------------------------

236: #pragma omp parallel for simd

237:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

238:         for (int j = 0; j < depth; ++j) {

239:           field.pressure(1 - j, k) = field.pressure(2 + j, k);

0x42ffc0 STP	X29, X30, [SP, #976]!

0x42ffc4 ADD	X29, SP, #0

0x42ffc8 STP	X19, X20, [SP, #16]

0x42ffcc LDR	W19, [X0, #8]

0x42ffd0 STP	X21, X22, [SP, #32]

0x42ffd4 ORR	X22, XZR, X0

0x42ffd8 LDR	W21, [X0, #16]

0x42ffdc SUB	W0, W19, W21

0x42ffe0 ADD	W19, W0, #1

0x42ffe4 BL	403530

0x42ffe8 ORR	W20, WZR, W0

0x42ffec BL	4033c0

0x42fff0 LDR	W2, [X22, #12]

0x42fff4 ORR	W1, WZR, W0

0x42fff8 ADD	W3, W21, W2

0x42fffc ADD	W4, W3, #2

0x430000 SUB	W5, W4, W19

0x430004 SDIV	W6, W5, W20

0x430008 MSUB	W7, W6, W20, W5

0x43000c CMP	W0, W7

0x430010 B.LT	4301e0

(474) 0x430014 MADD	W8, W6, W1, W7

(474) 0x430018 ADD	W9, W6, W8

(474) 0x43001c CMP	W8, W9

(474) 0x430020 B.GE	4301d0

(474) 0x430024 ADD	W10, W19, W8

(474) 0x430028 ADD	W19, W19, W9

(474) 0x43002c LDR	X11, [X22]

(474) 0x430030 CMP	W21, #0

(474) 0x430034 B.LE	4301d0

(474) 0x430038 LDR	X12, [X11, #112]

(474) 0x43003c SBFM	X4, X10, #0, #31

(474) 0x430040 SUB	W21, W21, #1

(474) 0x430044 MOVZ	W15, #0

(474) 0x430048 LDR	X14, [X11, #96]

(474) 0x43004c UBFM	X3, X12, #63, #62

(474) 0x430050 ADD	X13, X12, #8

(474) 0x430054 HINT	#0

(474) 0x430058 HINT	#0

(474) 0x43005c HINT	#0

  (476) 0x430060 MADD	X16, X14, X4, XZR

  (476) 0x430064 ADD	X17, X21, X16

  (476) 0x430068 ADD	X0, X12, X16,LSL #3

  (476) 0x43006c UBFM	X18, X16, #60, #59

  (476) 0x430070 ADD	X5, X13, X17,LSL #3

  (476) 0x430074 ADD	X1, X18, #8

  (476) 0x430078 SUB	X30, X5, X0

  (476) 0x43007c SUB	X22, X30, #8

  (476) 0x430080 UBFM	X20, X22, #3, #63

  (476) 0x430084 ADD	X2, X20, #1

  (476) 0x430088 ANDS	X6, X2, #4224

  (476) 0x43008c B.EQ	430138

  (476) 0x430090 CMP	X6, #1

  (476) 0x430094 B.EQ	430120

  (476) 0x430098 CMP	X6, #2

  (476) 0x43009c B.EQ	430110

  (476) 0x4300a0 CMP	X6, #3

  (476) 0x4300a4 B.EQ	430100

  (476) 0x4300a8 CMP	X6, #4

  (476) 0x4300ac B.EQ	4300f0

  (476) 0x4300b0 CMP	X6, #5

  (476) 0x4300b4 B.EQ	4300e0

  (476) 0x4300b8 CMP	X6, #6

  (476) 0x4300bc B.EQ	4300d0

  (476) 0x4300c0 LDR	D0, [X0, #16]

  (476) 0x4300c4 SUB	X7, X1, X0

  (476) 0x4300c8 ADD	X0, X0, #8

  (476) 0x4300cc STR	D0, [X7, X3]

  (476) 0x4300d0 LDR	D1, [X0, #16]

  (476) 0x4300d4 SUB	X8, X1, X0

  (476) 0x4300d8 ADD	X0, X0, #8

  (476) 0x4300dc STR	D1, [X8, X3]

  (476) 0x4300e0 LDR	D2, [X0, #16]

  (476) 0x4300e4 SUB	X9, X1, X0

  (476) 0x4300e8 ADD	X0, X0, #8

  (476) 0x4300ec STR	D2, [X9, X3]

  (476) 0x4300f0 LDR	D3, [X0, #16]

  (476) 0x4300f4 SUB	X10, X1, X0

  (476) 0x4300f8 ADD	X0, X0, #8

  (476) 0x4300fc STR	D3, [X10, X3]

  (476) 0x430100 LDR	D4, [X0, #16]

  (476) 0x430104 SUB	X11, X1, X0

  (476) 0x430108 ADD	X0, X0, #8

  (476) 0x43010c STR	D4, [X11, X3]

  (476) 0x430110 LDR	D5, [X0, #16]

  (476) 0x430114 SUB	X16, X1, X0

  (476) 0x430118 ADD	X0, X0, #8

  (476) 0x43011c STR	D5, [X16, X3]

  (476) 0x430120 LDR	D6, [X0, #16]

  (476) 0x430124 SUB	X17, X1, X0

  (476) 0x430128 ADD	X0, X0, #8

  (476) 0x43012c STR	D6, [X17, X3]

  (476) 0x430130 CMP	X5, X0

  (476) 0x430134 B.EQ	4301c0

    (475) 0x430138 LDR	D7, [X0, #16]

    (475) 0x43013c SUB	X6, X1, X0

    (475) 0x430140 ADD	X18, X0, #8

    (475) 0x430144 ADD	X11, X0, #16

    (475) 0x430148 SUB	X30, X1, X18

    (475) 0x43014c ADD	X10, X0, #24

    (475) 0x430150 SUB	X22, X1, X11

    (475) 0x430154 ADD	X9, X0, #32

    (475) 0x430158 SUB	X20, X1, X10

    (475) 0x43015c ADD	X8, X0, #40

    (475) 0x430160 SUB	X18, X1, X9

    (475) 0x430164 ADD	X7, X0, #48

    (475) 0x430168 SUB	X17, X1, X8

    (475) 0x43016c STR	D7, [X6, X3]

    (475) 0x430170 SUB	X16, X1, X7

    (475) 0x430174 ADD	X6, X0, #56

    (475) 0x430178 LDR	D16, [X0, #24]

    (475) 0x43017c SUB	X2, X1, X6

    (475) 0x430180 ADD	X0, X0, #64

    (475) 0x430184 STR	D16, [X30, X3]

    (475) 0x430188 LDR	D17, [X11, #16]

    (475) 0x43018c STR	D17, [X22, X3]

    (475) 0x430190 LDR	D18, [X10, #16]

    (475) 0x430194 STR	D18, [X20, X3]

    (475) 0x430198 LDR	D19, [X9, #16]

    (475) 0x43019c STR	D19, [X18, X3]

    (475) 0x4301a0 LDR	D20, [X8, #16]

    (475) 0x4301a4 STR	D20, [X17, X3]

    (475) 0x4301a8 LDR	D21, [X7, #16]

    (475) 0x4301ac STR	D21, [X16, X3]

    (475) 0x4301b0 LDR	D22, [X6, #16]

    (475) 0x4301b4 STR	D22, [X2, X3]

    (475) 0x4301b8 CMP	X5, X0

    (475) 0x4301bc B.NE	430138

  (476) 0x4301c0 ADD	X4, X4, #1

  (476) 0x4301c4 ADD	W5, W15, W4

  (476) 0x4301c8 CMP	W19, W5

  (476) 0x4301cc B.GT	430060

(474) 0x4301d0 LDP	X19, X20, [SP, #16]

(474) 0x4301d4 LDP	X21, X22, [SP, #32]

(474) 0x4301d8 LDP	X29, X30, [SP], #48

(474) 0x4301dc RET

(474) 0x4301e0 ADD	W6, W6, #1

(474) 0x4301e4 MOVZ	W7, #0

(474) 0x4301e8 B	430014

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:236-239
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:236-239

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ffc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4301e0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.18+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:236-239
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:236-239

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ffc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4301e0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.18+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.18]–	0.04	0.01
▼Loop 474 - update_halo.cpp:236-239 - exec–	0	0
▼Loop 476 - update_halo.cpp:238-239 - exec–	0.04	0.01
○Loop 475 - update_halo.cpp:238-239 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code