OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:193-196 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 193 - 196

--------------------------------------------------------------------------------

193: #pragma omp parallel for simd

194:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

195:         for (int j = 0; j < depth; ++j) {

196:           field.energy1(1 - j, k) = field.energy1(2 + j, k);

0x42f720 STP	X29, X30, [SP, #976]!

0x42f724 ADD	X29, SP, #0

0x42f728 STP	X19, X20, [SP, #16]

0x42f72c LDR	W19, [X0, #8]

0x42f730 STP	X21, X22, [SP, #32]

0x42f734 ORR	X22, XZR, X0

0x42f738 LDR	W21, [X0, #16]

0x42f73c SUB	W0, W19, W21

0x42f740 ADD	W19, W0, #1

0x42f744 BL	403530

0x42f748 ORR	W20, WZR, W0

0x42f74c BL	4033c0

0x42f750 LDR	W2, [X22, #12]

0x42f754 ORR	W1, WZR, W0

0x42f758 ADD	W3, W21, W2

0x42f75c ADD	W4, W3, #2

0x42f760 SUB	W5, W4, W19

0x42f764 SDIV	W6, W5, W20

0x42f768 MSUB	W7, W6, W20, W5

0x42f76c CMP	W0, W7

0x42f770 B.LT	42f940

(462) 0x42f774 MADD	W8, W6, W1, W7

(462) 0x42f778 ADD	W9, W6, W8

(462) 0x42f77c CMP	W8, W9

(462) 0x42f780 B.GE	42f930

(462) 0x42f784 ADD	W10, W19, W8

(462) 0x42f788 ADD	W19, W19, W9

(462) 0x42f78c LDR	X11, [X22]

(462) 0x42f790 CMP	W21, #0

(462) 0x42f794 B.LE	42f930

(462) 0x42f798 LDR	X12, [X11, #88]

(462) 0x42f79c SBFM	X4, X10, #0, #31

(462) 0x42f7a0 SUB	W21, W21, #1

(462) 0x42f7a4 MOVZ	W15, #0

(462) 0x42f7a8 LDR	X14, [X11, #72]

(462) 0x42f7ac UBFM	X3, X12, #63, #62

(462) 0x42f7b0 ADD	X13, X12, #8

(462) 0x42f7b4 HINT	#0

(462) 0x42f7b8 HINT	#0

(462) 0x42f7bc HINT	#0

  (464) 0x42f7c0 MADD	X16, X14, X4, XZR

  (464) 0x42f7c4 ADD	X17, X21, X16

  (464) 0x42f7c8 ADD	X0, X12, X16,LSL #3

  (464) 0x42f7cc UBFM	X18, X16, #60, #59

  (464) 0x42f7d0 ADD	X5, X13, X17,LSL #3

  (464) 0x42f7d4 ADD	X1, X18, #8

  (464) 0x42f7d8 SUB	X30, X5, X0

  (464) 0x42f7dc SUB	X22, X30, #8

  (464) 0x42f7e0 UBFM	X20, X22, #3, #63

  (464) 0x42f7e4 ADD	X2, X20, #1

  (464) 0x42f7e8 ANDS	X6, X2, #4224

  (464) 0x42f7ec B.EQ	42f898

  (464) 0x42f7f0 CMP	X6, #1

  (464) 0x42f7f4 B.EQ	42f880

  (464) 0x42f7f8 CMP	X6, #2

  (464) 0x42f7fc B.EQ	42f870

  (464) 0x42f800 CMP	X6, #3

  (464) 0x42f804 B.EQ	42f860

  (464) 0x42f808 CMP	X6, #4

  (464) 0x42f80c B.EQ	42f850

  (464) 0x42f810 CMP	X6, #5

  (464) 0x42f814 B.EQ	42f840

  (464) 0x42f818 CMP	X6, #6

  (464) 0x42f81c B.EQ	42f830

  (464) 0x42f820 LDR	D0, [X0, #16]

  (464) 0x42f824 SUB	X7, X1, X0

  (464) 0x42f828 ADD	X0, X0, #8

  (464) 0x42f82c STR	D0, [X7, X3]

  (464) 0x42f830 LDR	D1, [X0, #16]

  (464) 0x42f834 SUB	X8, X1, X0

  (464) 0x42f838 ADD	X0, X0, #8

  (464) 0x42f83c STR	D1, [X8, X3]

  (464) 0x42f840 LDR	D2, [X0, #16]

  (464) 0x42f844 SUB	X9, X1, X0

  (464) 0x42f848 ADD	X0, X0, #8

  (464) 0x42f84c STR	D2, [X9, X3]

  (464) 0x42f850 LDR	D3, [X0, #16]

  (464) 0x42f854 SUB	X10, X1, X0

  (464) 0x42f858 ADD	X0, X0, #8

  (464) 0x42f85c STR	D3, [X10, X3]

  (464) 0x42f860 LDR	D4, [X0, #16]

  (464) 0x42f864 SUB	X11, X1, X0

  (464) 0x42f868 ADD	X0, X0, #8

  (464) 0x42f86c STR	D4, [X11, X3]

  (464) 0x42f870 LDR	D5, [X0, #16]

  (464) 0x42f874 SUB	X16, X1, X0

  (464) 0x42f878 ADD	X0, X0, #8

  (464) 0x42f87c STR	D5, [X16, X3]

  (464) 0x42f880 LDR	D6, [X0, #16]

  (464) 0x42f884 SUB	X17, X1, X0

  (464) 0x42f888 ADD	X0, X0, #8

  (464) 0x42f88c STR	D6, [X17, X3]

  (464) 0x42f890 CMP	X5, X0

  (464) 0x42f894 B.EQ	42f920

    (463) 0x42f898 LDR	D7, [X0, #16]

    (463) 0x42f89c SUB	X6, X1, X0

    (463) 0x42f8a0 ADD	X18, X0, #8

    (463) 0x42f8a4 ADD	X11, X0, #16

    (463) 0x42f8a8 SUB	X30, X1, X18

    (463) 0x42f8ac ADD	X10, X0, #24

    (463) 0x42f8b0 SUB	X22, X1, X11

    (463) 0x42f8b4 ADD	X9, X0, #32

    (463) 0x42f8b8 SUB	X20, X1, X10

    (463) 0x42f8bc ADD	X8, X0, #40

    (463) 0x42f8c0 SUB	X18, X1, X9

    (463) 0x42f8c4 ADD	X7, X0, #48

    (463) 0x42f8c8 SUB	X17, X1, X8

    (463) 0x42f8cc STR	D7, [X6, X3]

    (463) 0x42f8d0 SUB	X16, X1, X7

    (463) 0x42f8d4 ADD	X6, X0, #56

    (463) 0x42f8d8 LDR	D16, [X0, #24]

    (463) 0x42f8dc SUB	X2, X1, X6

    (463) 0x42f8e0 ADD	X0, X0, #64

    (463) 0x42f8e4 STR	D16, [X30, X3]

    (463) 0x42f8e8 LDR	D17, [X11, #16]

    (463) 0x42f8ec STR	D17, [X22, X3]

    (463) 0x42f8f0 LDR	D18, [X10, #16]

    (463) 0x42f8f4 STR	D18, [X20, X3]

    (463) 0x42f8f8 LDR	D19, [X9, #16]

    (463) 0x42f8fc STR	D19, [X18, X3]

    (463) 0x42f900 LDR	D20, [X8, #16]

    (463) 0x42f904 STR	D20, [X17, X3]

    (463) 0x42f908 LDR	D21, [X7, #16]

    (463) 0x42f90c STR	D21, [X16, X3]

    (463) 0x42f910 LDR	D22, [X6, #16]

    (463) 0x42f914 STR	D22, [X2, X3]

    (463) 0x42f918 CMP	X5, X0

    (463) 0x42f91c B.NE	42f898

  (464) 0x42f920 ADD	X4, X4, #1

  (464) 0x42f924 ADD	W5, W15, W4

  (464) 0x42f928 CMP	W19, W5

  (464) 0x42f92c B.GT	42f7c0

(462) 0x42f930 LDP	X19, X20, [SP, #16]

(462) 0x42f934 LDP	X21, X22, [SP, #32]

(462) 0x42f938 LDP	X29, X30, [SP], #48

(462) 0x42f93c RET

(462) 0x42f940 ADD	W6, W6, #1

(462) 0x42f944 MOVZ	W7, #0

(462) 0x42f948 B	42f774

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:193-196
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:193-196

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42f940 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:193-196
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:193-196

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42f940 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.14]–	0.02	0
▼Loop 462 - update_halo.cpp:193-196 - exec–	0	0
▼Loop 464 - update_halo.cpp:195-196 - exec–	0.02	0
○Loop 463 - update_halo.cpp:195-196 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code