OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:173-176 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 173 - 176

--------------------------------------------------------------------------------

173: #pragma omp parallel for simd

174:       for (int j = (x_min - depth + 1); j < (x_max + depth + 2); j++) {

175:         for (int k = 0; k < depth; ++k) {

176:           field.energy1(j, 1 - k) = field.energy1(j, 2 + k);

0x42f2b0 STP	X29, X30, [SP, #976]!

0x42f2b4 ADD	X29, SP, #0

0x42f2b8 LDR	W6, [X0, #8]

0x42f2bc STP	X19, X20, [SP, #16]

0x42f2c0 LDR	W19, [X0, #16]

0x42f2c4 STP	X21, X22, [SP, #32]

0x42f2c8 ORR	X22, XZR, X0

0x42f2cc SUB	W0, W6, W19

0x42f2d0 ADD	W20, W0, #1

0x42f2d4 BL	403530

0x42f2d8 ORR	W21, WZR, W0

0x42f2dc BL	4033c0

0x42f2e0 LDR	W2, [X22, #12]

0x42f2e4 ORR	W1, WZR, W0

0x42f2e8 ADD	W3, W19, W2

0x42f2ec ADD	W4, W3, #2

0x42f2f0 SUB	W5, W4, W20

0x42f2f4 SDIV	W7, W5, W21

0x42f2f8 MSUB	W8, W7, W21, W5

0x42f2fc CMP	W0, W8

0x42f300 B.LT	42f4c8

(456) 0x42f304 MADD	W9, W7, W1, W8

(456) 0x42f308 ADD	W10, W7, W9

(456) 0x42f30c CMP	W9, W10

(456) 0x42f310 B.GE	42f4b8

(456) 0x42f314 ADD	W11, W20, W9

(456) 0x42f318 ADD	W6, W20, W10

(456) 0x42f31c LDR	X12, [X22]

(456) 0x42f320 CMP	W19, #0

(456) 0x42f324 B.LE	42f4b8

(456) 0x42f328 LDR	X21, [X12, #72]

(456) 0x42f32c SBFM	X4, X11, #0, #31

(456) 0x42f330 MOVZ	W30, #0

(456) 0x42f334 LDR	X20, [X12, #88]

(456) 0x42f338 UBFM	X0, X21, #61, #60

(456) 0x42f33c UBFM	X22, X21, #63, #62

  (458) 0x42f340 ADD	X13, X4, X22

  (458) 0x42f344 ADD	X14, X21, X4

  (458) 0x42f348 ANDS	W15, W19, #128

  (458) 0x42f34c ADD	X1, X20, X13,LSL #3

  (458) 0x42f350 MOVZ	W3, #0

  (458) 0x42f354 ADD	X2, X20, X14,LSL #3

  (458) 0x42f358 B.EQ	42f420

  (458) 0x42f35c CMP	W15, #1

  (458) 0x42f360 B.EQ	42f404

  (458) 0x42f364 CMP	W15, #2

  (458) 0x42f368 B.EQ	42f3f0

  (458) 0x42f36c CMP	W15, #3

  (458) 0x42f370 B.EQ	42f3dc

  (458) 0x42f374 CMP	W15, #4

  (458) 0x42f378 B.EQ	42f3c8

  (458) 0x42f37c CMP	W15, #5

  (458) 0x42f380 B.EQ	42f3b4

  (458) 0x42f384 CMP	W15, #6

  (458) 0x42f388 B.EQ	42f3a0

  (458) 0x42f38c LDR	D0, [X20, X13,LSL #3]

  (458) 0x42f390 ADD	X1, X1, X0

  (458) 0x42f394 SUB	X2, X2, X0

  (458) 0x42f398 MOVZ	W3, #1

  (458) 0x42f39c STR	D0, [X20, X14,LSL #3]

  (458) 0x42f3a0 LDR	D1, [X1]

  (458) 0x42f3a4 ADD	W3, W3, #1

  (458) 0x42f3a8 ADD	X1, X1, X0

  (458) 0x42f3ac STR	D1, [X2]

  (458) 0x42f3b0 SUB	X2, X2, X0

  (458) 0x42f3b4 LDR	D2, [X1]

  (458) 0x42f3b8 ADD	W3, W3, #1

  (458) 0x42f3bc ADD	X1, X1, X0

  (458) 0x42f3c0 STR	D2, [X2]

  (458) 0x42f3c4 SUB	X2, X2, X0

  (458) 0x42f3c8 LDR	D3, [X1]

  (458) 0x42f3cc ADD	W3, W3, #1

  (458) 0x42f3d0 ADD	X1, X1, X0

  (458) 0x42f3d4 STR	D3, [X2]

  (458) 0x42f3d8 SUB	X2, X2, X0

  (458) 0x42f3dc LDR	D4, [X1]

  (458) 0x42f3e0 ADD	W3, W3, #1

  (458) 0x42f3e4 ADD	X1, X1, X0

  (458) 0x42f3e8 STR	D4, [X2]

  (458) 0x42f3ec SUB	X2, X2, X0

  (458) 0x42f3f0 LDR	D5, [X1]

  (458) 0x42f3f4 ADD	W3, W3, #1

  (458) 0x42f3f8 ADD	X1, X1, X0

  (458) 0x42f3fc STR	D5, [X2]

  (458) 0x42f400 SUB	X2, X2, X0

  (458) 0x42f404 LDR	D6, [X1]

  (458) 0x42f408 ADD	W3, W3, #1

  (458) 0x42f40c ADD	X1, X1, X0

  (458) 0x42f410 STR	D6, [X2]

  (458) 0x42f414 SUB	X2, X2, X0

  (458) 0x42f418 CMP	W19, W3

  (458) 0x42f41c B.EQ	42f4a8

    (457) 0x42f420 LDR	D7, [X1]

    (457) 0x42f424 SUB	X18, X2, X0

    (457) 0x42f428 ADD	X17, X1, X0

    (457) 0x42f42c SUB	X16, X18, X0

    (457) 0x42f430 ADD	X15, X17, X0

    (457) 0x42f434 SUB	X14, X16, X0

    (457) 0x42f438 ADD	X13, X15, X0

    (457) 0x42f43c SUB	X12, X14, X0

    (457) 0x42f440 ADD	X11, X13, X0

    (457) 0x42f444 SUB	X10, X12, X0

    (457) 0x42f448 ADD	X9, X11, X0

    (457) 0x42f44c SUB	X8, X10, X0

    (457) 0x42f450 ADD	X7, X9, X0

    (457) 0x42f454 STR	D7, [X2]

    (457) 0x42f458 SUB	X5, X8, X0

    (457) 0x42f45c ADD	W3, W3, #8

    (457) 0x42f460 LDR	D16, [X1, X0]

    (457) 0x42f464 SUB	X2, X5, X0

    (457) 0x42f468 ADD	X1, X7, X0,LSL #1

    (457) 0x42f46c STR	D16, [X18]

    (457) 0x42f470 LDR	D17, [X17, X0]

    (457) 0x42f474 STR	D17, [X16]

    (457) 0x42f478 LDR	D18, [X15, X0]

    (457) 0x42f47c STR	D18, [X14]

    (457) 0x42f480 LDR	D19, [X13, X0]

    (457) 0x42f484 STR	D19, [X12]

    (457) 0x42f488 LDR	D20, [X11, X0]

    (457) 0x42f48c STR	D20, [X10]

    (457) 0x42f490 LDR	D21, [X9, X0]

    (457) 0x42f494 STR	D21, [X8]

    (457) 0x42f498 LDR	D22, [X7, X0]

    (457) 0x42f49c STR	D22, [X5]

    (457) 0x42f4a0 CMP	W19, W3

    (457) 0x42f4a4 B.NE	42f420

  (458) 0x42f4a8 ADD	X4, X4, #1

  (458) 0x42f4ac ADD	W3, W30, W4

  (458) 0x42f4b0 CMP	W6, W3

  (458) 0x42f4b4 B.GT	42f340

(456) 0x42f4b8 LDP	X19, X20, [SP, #16]

(456) 0x42f4bc LDP	X21, X22, [SP, #32]

(456) 0x42f4c0 LDP	X29, X30, [SP], #48

(456) 0x42f4c4 RET

(456) 0x42f4c8 ADD	W7, W7, #1

(456) 0x42f4cc MOVZ	W8, #0

(456) 0x42f4d0 B	42f304

0x42f4d4 HINT	#0

0x42f4d8 HINT	#0

0x42f4dc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:173-176
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:173-176

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W6, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W6, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W19, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W7, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W8, W7, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42f4c8 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:173-176
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:173-176

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W6, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W6, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W19, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W7, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W8, W7, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42f4c8 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.12]–	0.02	0
▼Loop 456 - update_halo.cpp:173-176 - exec–	0	0
▼Loop 458 - update_halo.cpp:175-176 - exec–	0.02	0
○Loop 457 - update_halo.cpp:175-176 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code