OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:150-153 [...]	Coverage: 0.07%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 150 - 153

--------------------------------------------------------------------------------

150: #pragma omp parallel for simd

151:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

152:         for (int j = 0; j < depth; ++j) {

153:           field.energy0(1 - j, k) = field.energy0(2 + j, k);

0x42ee80 STP	X29, X30, [SP, #976]!

0x42ee84 ADD	X29, SP, #0

0x42ee88 STP	X19, X20, [SP, #16]

0x42ee8c LDR	W19, [X0, #8]

0x42ee90 STP	X21, X22, [SP, #32]

0x42ee94 ORR	X22, XZR, X0

0x42ee98 LDR	W21, [X0, #16]

0x42ee9c SUB	W0, W19, W21

0x42eea0 ADD	W19, W0, #1

0x42eea4 BL	403530

0x42eea8 ORR	W20, WZR, W0

0x42eeac BL	4033c0

0x42eeb0 LDR	W2, [X22, #12]

0x42eeb4 ORR	W1, WZR, W0

0x42eeb8 ADD	W3, W21, W2

0x42eebc ADD	W4, W3, #2

0x42eec0 SUB	W5, W4, W19

0x42eec4 SDIV	W6, W5, W20

0x42eec8 MSUB	W7, W6, W20, W5

0x42eecc CMP	W0, W7

0x42eed0 B.LT	42f0a0

(450) 0x42eed4 MADD	W8, W6, W1, W7

(450) 0x42eed8 ADD	W9, W6, W8

(450) 0x42eedc CMP	W8, W9

(450) 0x42eee0 B.GE	42f090

(450) 0x42eee4 ADD	W10, W19, W8

(450) 0x42eee8 ADD	W19, W19, W9

(450) 0x42eeec LDR	X11, [X22]

(450) 0x42eef0 CMP	W21, #0

(450) 0x42eef4 B.LE	42f090

(450) 0x42eef8 LDR	X12, [X11, #64]

(450) 0x42eefc SBFM	X4, X10, #0, #31

(450) 0x42ef00 SUB	W21, W21, #1

(450) 0x42ef04 MOVZ	W15, #0

(450) 0x42ef08 LDR	X14, [X11, #48]

(450) 0x42ef0c UBFM	X3, X12, #63, #62

(450) 0x42ef10 ADD	X13, X12, #8

(450) 0x42ef14 HINT	#0

(450) 0x42ef18 HINT	#0

(450) 0x42ef1c HINT	#0

  (452) 0x42ef20 MADD	X16, X14, X4, XZR

  (452) 0x42ef24 ADD	X17, X21, X16

  (452) 0x42ef28 ADD	X0, X12, X16,LSL #3

  (452) 0x42ef2c UBFM	X18, X16, #60, #59

  (452) 0x42ef30 ADD	X5, X13, X17,LSL #3

  (452) 0x42ef34 ADD	X1, X18, #8

  (452) 0x42ef38 SUB	X30, X5, X0

  (452) 0x42ef3c SUB	X22, X30, #8

  (452) 0x42ef40 UBFM	X20, X22, #3, #63

  (452) 0x42ef44 ADD	X2, X20, #1

  (452) 0x42ef48 ANDS	X6, X2, #4224

  (452) 0x42ef4c B.EQ	42eff8

  (452) 0x42ef50 CMP	X6, #1

  (452) 0x42ef54 B.EQ	42efe0

  (452) 0x42ef58 CMP	X6, #2

  (452) 0x42ef5c B.EQ	42efd0

  (452) 0x42ef60 CMP	X6, #3

  (452) 0x42ef64 B.EQ	42efc0

  (452) 0x42ef68 CMP	X6, #4

  (452) 0x42ef6c B.EQ	42efb0

  (452) 0x42ef70 CMP	X6, #5

  (452) 0x42ef74 B.EQ	42efa0

  (452) 0x42ef78 CMP	X6, #6

  (452) 0x42ef7c B.EQ	42ef90

  (452) 0x42ef80 LDR	D0, [X0, #16]

  (452) 0x42ef84 SUB	X7, X1, X0

  (452) 0x42ef88 ADD	X0, X0, #8

  (452) 0x42ef8c STR	D0, [X7, X3]

  (452) 0x42ef90 LDR	D1, [X0, #16]

  (452) 0x42ef94 SUB	X8, X1, X0

  (452) 0x42ef98 ADD	X0, X0, #8

  (452) 0x42ef9c STR	D1, [X8, X3]

  (452) 0x42efa0 LDR	D2, [X0, #16]

  (452) 0x42efa4 SUB	X9, X1, X0

  (452) 0x42efa8 ADD	X0, X0, #8

  (452) 0x42efac STR	D2, [X9, X3]

  (452) 0x42efb0 LDR	D3, [X0, #16]

  (452) 0x42efb4 SUB	X10, X1, X0

  (452) 0x42efb8 ADD	X0, X0, #8

  (452) 0x42efbc STR	D3, [X10, X3]

  (452) 0x42efc0 LDR	D4, [X0, #16]

  (452) 0x42efc4 SUB	X11, X1, X0

  (452) 0x42efc8 ADD	X0, X0, #8

  (452) 0x42efcc STR	D4, [X11, X3]

  (452) 0x42efd0 LDR	D5, [X0, #16]

  (452) 0x42efd4 SUB	X16, X1, X0

  (452) 0x42efd8 ADD	X0, X0, #8

  (452) 0x42efdc STR	D5, [X16, X3]

  (452) 0x42efe0 LDR	D6, [X0, #16]

  (452) 0x42efe4 SUB	X17, X1, X0

  (452) 0x42efe8 ADD	X0, X0, #8

  (452) 0x42efec STR	D6, [X17, X3]

  (452) 0x42eff0 CMP	X5, X0

  (452) 0x42eff4 B.EQ	42f080

    (451) 0x42eff8 LDR	D7, [X0, #16]

    (451) 0x42effc SUB	X6, X1, X0

    (451) 0x42f000 ADD	X18, X0, #8

    (451) 0x42f004 ADD	X11, X0, #16

    (451) 0x42f008 SUB	X30, X1, X18

    (451) 0x42f00c ADD	X10, X0, #24

    (451) 0x42f010 SUB	X22, X1, X11

    (451) 0x42f014 ADD	X9, X0, #32

    (451) 0x42f018 SUB	X20, X1, X10

    (451) 0x42f01c ADD	X8, X0, #40

    (451) 0x42f020 SUB	X18, X1, X9

    (451) 0x42f024 ADD	X7, X0, #48

    (451) 0x42f028 SUB	X17, X1, X8

    (451) 0x42f02c STR	D7, [X6, X3]

    (451) 0x42f030 SUB	X16, X1, X7

    (451) 0x42f034 ADD	X6, X0, #56

    (451) 0x42f038 LDR	D16, [X0, #24]

    (451) 0x42f03c SUB	X2, X1, X6

    (451) 0x42f040 ADD	X0, X0, #64

    (451) 0x42f044 STR	D16, [X30, X3]

    (451) 0x42f048 LDR	D17, [X11, #16]

    (451) 0x42f04c STR	D17, [X22, X3]

    (451) 0x42f050 LDR	D18, [X10, #16]

    (451) 0x42f054 STR	D18, [X20, X3]

    (451) 0x42f058 LDR	D19, [X9, #16]

    (451) 0x42f05c STR	D19, [X18, X3]

    (451) 0x42f060 LDR	D20, [X8, #16]

    (451) 0x42f064 STR	D20, [X17, X3]

    (451) 0x42f068 LDR	D21, [X7, #16]

    (451) 0x42f06c STR	D21, [X16, X3]

    (451) 0x42f070 LDR	D22, [X6, #16]

    (451) 0x42f074 STR	D22, [X2, X3]

    (451) 0x42f078 CMP	X5, X0

    (451) 0x42f07c B.NE	42eff8

  (452) 0x42f080 ADD	X4, X4, #1

  (452) 0x42f084 ADD	W5, W15, W4

  (452) 0x42f088 CMP	W19, W5

  (452) 0x42f08c B.GT	42ef20

(450) 0x42f090 LDP	X19, X20, [SP, #16]

(450) 0x42f094 LDP	X21, X22, [SP, #32]

(450) 0x42f098 LDP	X29, X30, [SP], #48

(450) 0x42f09c RET

(450) 0x42f0a0 ADD	W6, W6, #1

(450) 0x42f0a4 MOVZ	W7, #0

(450) 0x42f0a8 B	42eed4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:150-153
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:150-153

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ee80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42f0a0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.10+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:150-153
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:150-153

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ee80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42f0a0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.10+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.10]–	0.07	0.02
▼Loop 450 - update_halo.cpp:150-153 - exec–	0	0
▼Loop 452 - update_halo.cpp:152-153 - exec–	0.07	0.01
○Loop 451 - update_halo.cpp:152-153 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code