OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:117-120 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 117 - 120

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd

118:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

119:         for (int j = 0; j < depth; ++j) {

120:           field.density1(x_max + 2 + j, k) = field.density1(x_max + 1 - j, k);

0x42e80c STP	X29, X30, [SP, #976]!

0x42e810 ADD	X29, SP, #0

0x42e814 STP	X19, X20, [SP, #16]

0x42e818 LDR	W19, [X0, #12]

0x42e81c STP	X21, X22, [SP, #32]

0x42e820 ORR	X22, XZR, X0

0x42e824 LDR	W20, [X0, #20]

0x42e828 SUB	W0, W19, W20

0x42e82c ADD	W19, W0, #1

0x42e830 BL	403530

0x42e834 ORR	W21, WZR, W0

0x42e838 BL	4033c0

0x42e83c LDR	W2, [X22, #16]

0x42e840 ORR	W1, WZR, W0

0x42e844 ADD	W3, W20, W2

0x42e848 ADD	W4, W3, #2

0x42e84c SUB	W5, W4, W19

0x42e850 SDIV	W6, W5, W21

0x42e854 MSUB	W7, W6, W21, W5

0x42e858 CMP	W0, W7

0x42e85c B.LT	42ea04

  (443) 0x42e860 MADD	W8, W6, W1, W7

  (443) 0x42e864 ADD	W9, W6, W8

  (443) 0x42e868 CMP	W8, W9

  (443) 0x42e86c B.GE	42e9f4

  (443) 0x42e870 ADD	W10, W19, W8

  (443) 0x42e874 LDR	W13, [X22, #8]

  (443) 0x42e878 ADD	W19, W19, W9

  (443) 0x42e87c LDR	X11, [X22]

  (443) 0x42e880 CMP	W20, #0

  (443) 0x42e884 B.LE	42e9f4

(441) 0x42e888 ADD	W14, W13, #1

(441) 0x42e88c SBFM	X5, X10, #0, #31

(441) 0x42e890 LDR	X16, [X11, #24]

(441) 0x42e894 SBFM	X14, X14, #0, #31

(441) 0x42e898 SBFM	X13, X13, #0, #31

(441) 0x42e89c MOVZ	W15, #0

(441) 0x42e8a0 LDR	X6, [X11, #40]

(441) 0x42e8a4 MADD	X12, X16, X5, XZR

(441) 0x42e8a8 SUB	W17, W20, #1

(441) 0x42e8ac MOVZ	X0, #1

(441) 0x42e8b0 AND	W18, W17, #128

(441) 0x42e8b4 ADD	X30, X14, X12

(441) 0x42e8b8 ADD	X22, X13, X12

(441) 0x42e8bc UBFM	X21, X22, #61, #60

(441) 0x42e8c0 ADD	X4, X6, X30,LSL #3

(441) 0x42e8c4 LDR	D0, [X6, X30,LSL #3]

(441) 0x42e8c8 ADD	X2, X21, #16

(441) 0x42e8cc ADD	X3, X6, X2

(441) 0x42e8d0 SUB	X1, X4, #8

(441) 0x42e8d4 STR	D0, [X6, X2]

(441) 0x42e8d8 CMP	W20, #1

(441) 0x42e8dc B.LE	42e9e4

(441) 0x42e8e0 CBZ	W18, 42e974

0x42e8e4 CMP	W18, #1

0x42e8e8 B.EQ	42e960

0x42e8ec CMP	W18, #2

0x42e8f0 B.EQ	42e954

0x42e8f4 CMP	W18, #3

0x42e8f8 B.EQ	42e948

0x42e8fc CMP	W18, #4

0x42e900 B.EQ	42e93c

0x42e904 CMP	W18, #5

0x42e908 B.EQ	42e930

0x42e90c CMP	W18, #6

0x42e910 B.EQ	42e924

0x42e914 LDUR	D1, [X4, #504]

0x42e918 SUB	X1, X1, #8

0x42e91c MOVZ	X0, #2

0x42e920 STR	D1, [X3, #8]

0x42e924 LDR	D2, [X1], #504

0x42e928 STR	D2, [X3, X0,LSL #3]

0x42e92c ADD	X0, X0, #1

0x42e930 LDR	D3, [X1], #504

0x42e934 STR	D3, [X3, X0,LSL #3]

0x42e938 ADD	X0, X0, #1

0x42e93c LDR	D4, [X1], #504

0x42e940 STR	D4, [X3, X0,LSL #3]

0x42e944 ADD	X0, X0, #1

0x42e948 LDR	D5, [X1], #504

0x42e94c STR	D5, [X3, X0,LSL #3]

0x42e950 ADD	X0, X0, #1

0x42e954 LDR	D6, [X1], #504

0x42e958 STR	D6, [X3, X0,LSL #3]

0x42e95c ADD	X0, X0, #1

0x42e960 LDR	D7, [X1], #504

0x42e964 STR	D7, [X3, X0,LSL #3]

0x42e968 ADD	X0, X0, #1

0x42e96c CMP	W20, W0

0x42e970 B.LE	42e9e4

  (442) 0x42e974 ORR	X17, XZR, X1

  (442) 0x42e978 ADD	X18, X0, #1

  (442) 0x42e97c ADD	X12, X0, #2

  (442) 0x42e980 ADD	X11, X0, #3

  (442) 0x42e984 LDR	D16, [X17], #504

  (442) 0x42e988 ADD	X10, X0, #4

  (442) 0x42e98c ADD	X9, X0, #5

  (442) 0x42e990 ADD	X8, X0, #6

  (442) 0x42e994 ADD	X7, X0, #7

  (442) 0x42e998 SUB	X1, X1, #64

  (442) 0x42e99c STR	D16, [X3, X0,LSL #3]

  (442) 0x42e9a0 ADD	X0, X0, #8

  (442) 0x42e9a4 LDR	D17, [X1, #56]

  (442) 0x42e9a8 STR	D17, [X3, X18,LSL #3]

  (442) 0x42e9ac LDUR	D18, [X17, #504]

  (442) 0x42e9b0 STR	D18, [X3, X12,LSL #3]

  (442) 0x42e9b4 LDR	D19, [X1, #40]

  (442) 0x42e9b8 STR	D19, [X3, X11,LSL #3]

  (442) 0x42e9bc LDR	D20, [X1, #32]

  (442) 0x42e9c0 STR	D20, [X3, X10,LSL #3]

  (442) 0x42e9c4 LDR	D21, [X1, #24]

  (442) 0x42e9c8 STR	D21, [X3, X9,LSL #3]

  (442) 0x42e9cc LDR	D22, [X1, #16]

  (442) 0x42e9d0 STR	D22, [X3, X8,LSL #3]

  (442) 0x42e9d4 LDR	D23, [X1, #8]

  (442) 0x42e9d8 STR	D23, [X3, X7,LSL #3]

  (442) 0x42e9dc CMP	W20, W0

  (442) 0x42e9e0 B.GT	42e974

(441) 0x42e9e4 ADD	X5, X5, #1

(441) 0x42e9e8 ADD	W30, W15, W5

(441) 0x42e9ec CMP	W19, W30

(441) 0x42e9f0 B.GT	42e8a4

  (443) 0x42e9f4 LDP	X19, X20, [SP, #16]

  (443) 0x42e9f8 LDP	X21, X22, [SP, #32]

  (443) 0x42e9fc LDP	X29, X30, [SP], #48

  (443) 0x42ea00 RET

  (443) 0x42ea04 ADD	W6, W6, #1

  (443) 0x42ea08 MOVZ	W7, #0

  (443) 0x42ea0c B	42e860

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:117-120
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:117-120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 5.17 cycles (1.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 9.00 to 1.46 cycles (6.17x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50
cycles	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	7.13
Overall L1	9.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

7% of peak load performance is reached (7.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e80c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 42ea04 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e960 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e954 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e948 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e93c <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e930 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e924 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D1, [X4, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D1, [X3, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDR D2, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 42e9e4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:117-120
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:117-120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 5.17 cycles (1.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50
cycles	5.00	5.00	9.00	9.00	9.00	9.00	3.50	3.50	0.00	0.00	6.67	6.67	6.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	7.13
Overall L1	9.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

7% of peak load performance is reached (7.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e80c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 42ea04 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e960 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e954 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e948 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e93c <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e930 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e924 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D1, [X4, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D1, [X3, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDR D2, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X1], #504	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 42e9e4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.7+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.7]–	0.02	0
▼Loop 441 - update_halo.cpp:117-120 - exec–	0.02	0
○Loop 443 - update_halo.cpp:117-120 - exec	0	0
○Loop 442 - update_halo.cpp:119-120 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code