OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:107-110 [...]	Coverage: 0.07%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 107 - 110

--------------------------------------------------------------------------------

107: #pragma omp parallel for simd

108:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

109:         for (int j = 0; j < depth; ++j) {

110:           field.density1(1 - j, k) = field.density1(2 + j, k);

0x42e5e0 STP	X29, X30, [SP, #976]!

0x42e5e4 ADD	X29, SP, #0

0x42e5e8 STP	X19, X20, [SP, #16]

0x42e5ec LDR	W19, [X0, #8]

0x42e5f0 STP	X21, X22, [SP, #32]

0x42e5f4 ORR	X22, XZR, X0

0x42e5f8 LDR	W21, [X0, #16]

0x42e5fc SUB	W0, W19, W21

0x42e600 ADD	W19, W0, #1

0x42e604 BL	403530

0x42e608 ORR	W20, WZR, W0

0x42e60c BL	4033c0

0x42e610 LDR	W2, [X22, #12]

0x42e614 ORR	W1, WZR, W0

0x42e618 ADD	W3, W21, W2

0x42e61c ADD	W4, W3, #2

0x42e620 SUB	W5, W4, W19

0x42e624 SDIV	W6, W5, W20

0x42e628 MSUB	W7, W6, W20, W5

0x42e62c CMP	W0, W7

0x42e630 B.LT	42e800

(438) 0x42e634 MADD	W8, W6, W1, W7

(438) 0x42e638 ADD	W9, W6, W8

(438) 0x42e63c CMP	W8, W9

(438) 0x42e640 B.GE	42e7f0

(438) 0x42e644 ADD	W10, W19, W8

(438) 0x42e648 ADD	W19, W19, W9

(438) 0x42e64c LDR	X11, [X22]

(438) 0x42e650 CMP	W21, #0

(438) 0x42e654 B.LE	42e7f0

(438) 0x42e658 LDR	X12, [X11, #40]

(438) 0x42e65c SBFM	X4, X10, #0, #31

(438) 0x42e660 SUB	W21, W21, #1

(438) 0x42e664 MOVZ	W15, #0

(438) 0x42e668 LDR	X14, [X11, #24]

(438) 0x42e66c UBFM	X3, X12, #63, #62

(438) 0x42e670 ADD	X13, X12, #8

(438) 0x42e674 HINT	#0

(438) 0x42e678 HINT	#0

(438) 0x42e67c HINT	#0

  (440) 0x42e680 MADD	X16, X14, X4, XZR

  (440) 0x42e684 ADD	X17, X21, X16

  (440) 0x42e688 ADD	X0, X12, X16,LSL #3

  (440) 0x42e68c UBFM	X18, X16, #60, #59

  (440) 0x42e690 ADD	X5, X13, X17,LSL #3

  (440) 0x42e694 ADD	X1, X18, #8

  (440) 0x42e698 SUB	X30, X5, X0

  (440) 0x42e69c SUB	X22, X30, #8

  (440) 0x42e6a0 UBFM	X20, X22, #3, #63

  (440) 0x42e6a4 ADD	X2, X20, #1

  (440) 0x42e6a8 ANDS	X6, X2, #4224

  (440) 0x42e6ac B.EQ	42e758

  (440) 0x42e6b0 CMP	X6, #1

  (440) 0x42e6b4 B.EQ	42e740

  (440) 0x42e6b8 CMP	X6, #2

  (440) 0x42e6bc B.EQ	42e730

  (440) 0x42e6c0 CMP	X6, #3

  (440) 0x42e6c4 B.EQ	42e720

  (440) 0x42e6c8 CMP	X6, #4

  (440) 0x42e6cc B.EQ	42e710

  (440) 0x42e6d0 CMP	X6, #5

  (440) 0x42e6d4 B.EQ	42e700

  (440) 0x42e6d8 CMP	X6, #6

  (440) 0x42e6dc B.EQ	42e6f0

  (440) 0x42e6e0 LDR	D0, [X0, #16]

  (440) 0x42e6e4 SUB	X7, X1, X0

  (440) 0x42e6e8 ADD	X0, X0, #8

  (440) 0x42e6ec STR	D0, [X7, X3]

  (440) 0x42e6f0 LDR	D1, [X0, #16]

  (440) 0x42e6f4 SUB	X8, X1, X0

  (440) 0x42e6f8 ADD	X0, X0, #8

  (440) 0x42e6fc STR	D1, [X8, X3]

  (440) 0x42e700 LDR	D2, [X0, #16]

  (440) 0x42e704 SUB	X9, X1, X0

  (440) 0x42e708 ADD	X0, X0, #8

  (440) 0x42e70c STR	D2, [X9, X3]

  (440) 0x42e710 LDR	D3, [X0, #16]

  (440) 0x42e714 SUB	X10, X1, X0

  (440) 0x42e718 ADD	X0, X0, #8

  (440) 0x42e71c STR	D3, [X10, X3]

  (440) 0x42e720 LDR	D4, [X0, #16]

  (440) 0x42e724 SUB	X11, X1, X0

  (440) 0x42e728 ADD	X0, X0, #8

  (440) 0x42e72c STR	D4, [X11, X3]

  (440) 0x42e730 LDR	D5, [X0, #16]

  (440) 0x42e734 SUB	X16, X1, X0

  (440) 0x42e738 ADD	X0, X0, #8

  (440) 0x42e73c STR	D5, [X16, X3]

  (440) 0x42e740 LDR	D6, [X0, #16]

  (440) 0x42e744 SUB	X17, X1, X0

  (440) 0x42e748 ADD	X0, X0, #8

  (440) 0x42e74c STR	D6, [X17, X3]

  (440) 0x42e750 CMP	X5, X0

  (440) 0x42e754 B.EQ	42e7e0

    (439) 0x42e758 LDR	D7, [X0, #16]

    (439) 0x42e75c SUB	X6, X1, X0

    (439) 0x42e760 ADD	X18, X0, #8

    (439) 0x42e764 ADD	X11, X0, #16

    (439) 0x42e768 SUB	X30, X1, X18

    (439) 0x42e76c ADD	X10, X0, #24

    (439) 0x42e770 SUB	X22, X1, X11

    (439) 0x42e774 ADD	X9, X0, #32

    (439) 0x42e778 SUB	X20, X1, X10

    (439) 0x42e77c ADD	X8, X0, #40

    (439) 0x42e780 SUB	X18, X1, X9

    (439) 0x42e784 ADD	X7, X0, #48

    (439) 0x42e788 SUB	X17, X1, X8

    (439) 0x42e78c STR	D7, [X6, X3]

    (439) 0x42e790 SUB	X16, X1, X7

    (439) 0x42e794 ADD	X6, X0, #56

    (439) 0x42e798 LDR	D16, [X0, #24]

    (439) 0x42e79c SUB	X2, X1, X6

    (439) 0x42e7a0 ADD	X0, X0, #64

    (439) 0x42e7a4 STR	D16, [X30, X3]

    (439) 0x42e7a8 LDR	D17, [X11, #16]

    (439) 0x42e7ac STR	D17, [X22, X3]

    (439) 0x42e7b0 LDR	D18, [X10, #16]

    (439) 0x42e7b4 STR	D18, [X20, X3]

    (439) 0x42e7b8 LDR	D19, [X9, #16]

    (439) 0x42e7bc STR	D19, [X18, X3]

    (439) 0x42e7c0 LDR	D20, [X8, #16]

    (439) 0x42e7c4 STR	D20, [X17, X3]

    (439) 0x42e7c8 LDR	D21, [X7, #16]

    (439) 0x42e7cc STR	D21, [X16, X3]

    (439) 0x42e7d0 LDR	D22, [X6, #16]

    (439) 0x42e7d4 STR	D22, [X2, X3]

    (439) 0x42e7d8 CMP	X5, X0

    (439) 0x42e7dc B.NE	42e758

  (440) 0x42e7e0 ADD	X4, X4, #1

  (440) 0x42e7e4 ADD	W5, W15, W4

  (440) 0x42e7e8 CMP	W19, W5

  (440) 0x42e7ec B.GT	42e680

(438) 0x42e7f0 LDP	X19, X20, [SP, #16]

(438) 0x42e7f4 LDP	X21, X22, [SP, #32]

(438) 0x42e7f8 LDP	X29, X30, [SP], #48

(438) 0x42e7fc RET

(438) 0x42e800 ADD	W6, W6, #1

(438) 0x42e804 MOVZ	W7, #0

(438) 0x42e808 B	42e634

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:107-110
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:107-110

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e5e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e800 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.6+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:107-110
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:107-110

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e5e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e800 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.6+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.6]–	0.07	0.02
▼Loop 438 - update_halo.cpp:107-110 - exec–	0	0
▼Loop 440 - update_halo.cpp:109-110 - exec–	0.07	0.01
○Loop 439 - update_halo.cpp:109-110 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code