OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage: 4.13%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

0x42c740 STP	X29, X30, [SP, #736]!

0x42c744 ADD	X29, SP, #0

0x42c748 STP	X19, X20, [SP, #16]

0x42c74c ORR	X20, XZR, X0

0x42c750 STP	X21, X22, [SP, #32]

0x42c754 LDP	W22, W1, [X0, #120]

0x42c758 LDR	W0, [X0, #112]

0x42c75c LDR	W2, [X20, #116]

0x42c760 ADD	W3, W1, #2

0x42c764 ADD	W22, W22, #1

0x42c768 ADD	W4, W0, #1

0x42c76c STP	W3, W4, [SP, #240]

0x42c770 CMP	W22, W3

0x42c774 B.GE	42cbec

0x42c778 ADD	W19, W2, #2

0x42c77c STP	X23, X24, [SP, #48]

0x42c780 SUB	W23, W3, W22

0x42c784 CMP	W4, W19

0x42c788 B.GE	42cbfc

0x42c78c SUB	W5, W19, W4

0x42c790 MADD	W24, W23, W5, WZR

0x42c794 STR	W5, [SP, #248]

0x42c798 BL	403530

0x42c79c ORR	W21, WZR, W0

0x42c7a0 BL	4033c0

0x42c7a4 UDIV	W7, W24, W21

0x42c7a8 ORR	W6, WZR, W0

0x42c7ac MSUB	W8, W7, W21, W24

0x42c7b0 CMP	W0, W8

0x42c7b4 B.CC	42cc10

  (396) 0x42c7b8 MADD	W8, W7, W6, W8

  (396) 0x42c7bc ADD	W9, W7, W8

  (396) 0x42c7c0 STR	W9, [SP, #252]

  (396) 0x42c7c4 CMP	W8, W9

  (396) 0x42c7c8 B.CS	42cbfc

(398) 0x42c7cc LDR	W10, [SP, #248]

(398) 0x42c7d0 FMOV	D0, #0.2500000

(398) 0x42c7d4 PTRUE	P1.B, ALL

(398) 0x42c7d8 STP	X25, X26, [SP, #64]

(398) 0x42c7dc FDUP	Z5.D, #112

(398) 0x42c7e0 LDR	W16, [SP, #244]

(398) 0x42c7e4 UDIV	W11, W8, W10

(398) 0x42c7e8 STP	X27, X28, [SP, #80]

(398) 0x42c7ec LDR	X25, [X20, #24]

(398) 0x42c7f0 LDR	X26, [X20, #64]

(398) 0x42c7f4 LDR	X14, [X20, #8]

(398) 0x42c7f8 LDR	X17, [X20, #16]

(398) 0x42c7fc MSUB	W12, W11, W10, W8

(398) 0x42c800 ADD	W13, W11, W22

(398) 0x42c804 STP	X25, X26, [SP, #120]

(398) 0x42c808 SBFM	X28, X13, #0, #31

(398) 0x42c80c ADD	W9, W12, W16

(398) 0x42c810 LDR	X27, [X20, #32]

(398) 0x42c814 SUB	W25, W19, W9

(398) 0x42c818 STR	X14, [SP, #104]

(398) 0x42c81c LDR	X22, [X20, #40]

(398) 0x42c820 CMP	W7, W25

(398) 0x42c824 CSEL	W2, W7, W25, #9

(398) 0x42c828 ADD	W23, W8, W2

(398) 0x42c82c STR	X17, [SP, #272]

(398) 0x42c830 LDR	X15, [X20, #48]

(398) 0x42c834 LDR	X18, [X20, #56]

(398) 0x42c838 STR	X22, [SP, #168]

(398) 0x42c83c LDR	X30, [X20, #72]

(398) 0x42c840 STR	X15, [SP, #152]

(398) 0x42c844 LDR	X0, [X20, #80]

(398) 0x42c848 STR	X18, [SP, #160]

(398) 0x42c84c LDR	X4, [X20, #88]

(398) 0x42c850 STP	X27, X30, [SP, #136]

(398) 0x42c854 LDR	X19, [X20, #96]

(398) 0x42c858 STR	X0, [SP, #256]

(398) 0x42c85c LDR	D4, [X20]

(398) 0x42c860 STR	X4, [SP, #264]

(398) 0x42c864 LDR	X20, [X20, #104]

(398) 0x42c868 STR	X19, [SP, #280]

(398) 0x42c86c FMUL	D1, D4, D0

(398) 0x42c870 DUP	Z16.D, Z1.D[0]

(398) 0x42c874 STR	X20, [SP, #112]

(398) 0x42c878 STR	W23, [SP, #100]

(398) 0x42c87c CMP	W8, W23

(398) 0x42c880 B.CS	42cbc8

  (399) 0x42c884 LDP	X10, X12, [SP, #256]

  (399) 0x42c888 SBFM	X1, X9, #0, #31

  (399) 0x42c88c ORR	W2, WZR, W2

  (399) 0x42c890 ADD	X3, X1, #1

  (399) 0x42c894 WHILELO	P0.D, XZR, X2

  (399) 0x42c898 LDP	X24, X21, [SP, #104]

  (399) 0x42c89c LDP	X27, X0, [SP, #272]

  (399) 0x42c8a0 LDP	X8, X18, [SP, #128]

  (399) 0x42c8a4 LDR	X13, [X10]

  (399) 0x42c8a8 LDR	X9, [X21]

  (399) 0x42c8ac LDR	X6, [X0]

  (399) 0x42c8b0 MADD	X14, X28, X13, XZR

  (399) 0x42c8b4 LDR	X20, [X12]

  (399) 0x42c8b8 MADD	X11, X28, X9, XZR

  (399) 0x42c8bc LDR	X15, [X10, #16]

  (399) 0x42c8c0 ADD	X16, X13, X14

  (399) 0x42c8c4 ADD	X5, X14, X3

  (399) 0x42c8c8 MADD	X26, X28, X6, XZR

  (399) 0x42c8cc ADD	X4, X16, X3

  (399) 0x42c8d0 ADD	X17, X14, X1

  (399) 0x42c8d4 LDR	X10, [X12, #16]

  (399) 0x42c8d8 ADD	X25, X16, X1

  (399) 0x42c8dc MADD	X12, X28, X20, XZR

  (399) 0x42c8e0 STR	X5, [SP, #184]

  (399) 0x42c8e4 ADD	X7, X6, X26

  (399) 0x42c8e8 ADD	X6, X9, X11

  (399) 0x42c8ec LDR	X19, [X8]

  (399) 0x42c8f0 ADD	X9, X15, X4,LSL #3

  (399) 0x42c8f4 ADD	X22, X7, X1

  (399) 0x42c8f8 ADD	X7, X7, X3

  (399) 0x42c8fc LDR	X4, [X27]

  (399) 0x42c900 ADD	X8, X20, X12

  (399) 0x42c904 ADD	X14, X12, X1

  (399) 0x42c908 ADD	X13, X8, X3

  (399) 0x42c90c ADD	X23, X8, X1

  (399) 0x42c910 ADD	X20, X10, X14,LSL #3

  (399) 0x42c914 ADD	X8, X10, X13,LSL #3

  (399) 0x42c918 LDR	X5, [SP, #120]

  (399) 0x42c91c ADD	X16, X12, X3

  (399) 0x42c920 ADD	X12, X10, X16,LSL #3

  (399) 0x42c924 LDR	X30, [SP, #144]

  (399) 0x42c928 ADD	X23, X10, X23,LSL #3

  (399) 0x42c92c LDR	X13, [SP, #152]

  (399) 0x42c930 LDR	X21, [X24]

  (399) 0x42c934 ADD	X24, X15, X25,LSL #3

  (399) 0x42c938 ADD	X25, X15, X17,LSL #3

  (399) 0x42c93c MADD	X17, X28, X19, X1

  (399) 0x42c940 LDR	X30, [X30]

  (399) 0x42c944 MADD	X19, X28, X4, XZR

  (399) 0x42c948 LDR	X13, [X13]

  (399) 0x42c94c MADD	X14, X28, X21, XZR

  (399) 0x42c950 ADD	X10, X4, X19

  (399) 0x42c954 LDR	X4, [X5]

  (399) 0x42c958 ADD	X16, X19, X1

  (399) 0x42c95c ADD	X10, X10, X1

  (399) 0x42c960 LDR	X5, [X18]

  (399) 0x42c964 ADD	X18, X26, X1

  (399) 0x42c968 ADD	X26, X26, X3

  (399) 0x42c96c ADD	X19, X14, X3

  (399) 0x42c970 ADD	X14, X14, X1

  (399) 0x42c974 LDR	X27, [X27, #16]

  (399) 0x42c978 MADD	X21, X28, X4, X1

  (399) 0x42c97c MADD	X4, X28, X30, X1

  (399) 0x42c980 MADD	X30, X28, X13, X1

  (399) 0x42c984 LDR	X13, [X0, #16]

  (399) 0x42c988 MADD	X5, X28, X5, X1

  (399) 0x42c98c STR	X21, [SP, #192]

  (399) 0x42c990 ADD	X21, X6, X1

  (399) 0x42c994 ADD	X10, X27, X10,LSL #3

  (399) 0x42c998 ADD	X6, X6, X3

  (399) 0x42c99c ADD	X3, X11, X3

  (399) 0x42c9a0 ADD	X16, X27, X16,LSL #3

  (399) 0x42c9a4 ADD	X11, X11, X1

  (399) 0x42c9a8 STP	X5, X4, [SP, #208]

  (399) 0x42c9ac ADD	X22, X13, X22,LSL #3

  (399) 0x42c9b0 ADD	X7, X13, X7,LSL #3

  (399) 0x42c9b4 ADD	X18, X13, X18,LSL #3

  (399) 0x42c9b8 ADD	X13, X13, X26,LSL #3

  (399) 0x42c9bc LDR	X26, [SP, #160]

  (399) 0x42c9c0 LDR	X5, [X26]

  (399) 0x42c9c4 LDR	X0, [SP, #168]

  (399) 0x42c9c8 LDR	X4, [SP, #112]

  (399) 0x42c9cc MADD	X5, X28, X5, X1

  (399) 0x42c9d0 LDR	X26, [SP, #120]

  (399) 0x42c9d4 LDR	X0, [X0]

  (399) 0x42c9d8 LDR	X27, [X4, #16]

  (399) 0x42c9dc MADD	X4, X28, X0, X1

  (399) 0x42c9e0 LDR	X1, [SP, #104]

  (399) 0x42c9e4 ADD	X21, X27, X21,LSL #3

  (399) 0x42c9e8 ADD	X6, X27, X6,LSL #3

  (399) 0x42c9ec ADD	X3, X27, X3,LSL #3

  (399) 0x42c9f0 LDR	X0, [X1, #16]

  (399) 0x42c9f4 ADD	X11, X27, X11,LSL #3

  (399) 0x42c9f8 LDR	X1, [X26, #16]

  (399) 0x42c9fc STR	X0, [SP, #176]

  (399) 0x42ca00 LDR	X27, [SP, #176]

  (399) 0x42ca04 STR	X1, [SP, #200]

  (399) 0x42ca08 LDR	X0, [SP, #184]

  (399) 0x42ca0c LDR	X26, [SP, #200]

  (399) 0x42ca10 ADD	X14, X27, X14,LSL #3

  (399) 0x42ca14 ADD	X19, X27, X19,LSL #3

  (399) 0x42ca18 LDR	X27, [SP, #128]

  (399) 0x42ca1c ADD	X15, X15, X0,LSL #3

  (399) 0x42ca20 LDR	X0, [SP, #136]

  (399) 0x42ca24 LDR	X1, [X27, #16]

  (399) 0x42ca28 LDR	X27, [X0, #16]

  (399) 0x42ca2c LDR	X0, [SP, #152]

  (399) 0x42ca30 STR	X1, [SP, #184]

  (399) 0x42ca34 LDR	X1, [SP, #144]

  (399) 0x42ca38 STR	X27, [SP, #176]

  (399) 0x42ca3c LDR	X27, [X1, #16]

  (399) 0x42ca40 LDR	X1, [X0, #16]

  (399) 0x42ca44 LDR	X0, [SP, #192]

  (399) 0x42ca48 STR	X27, [SP, #224]

  (399) 0x42ca4c LDR	X27, [SP, #160]

  (399) 0x42ca50 STR	X1, [SP, #232]

  (399) 0x42ca54 ADD	X1, X26, X0,LSL #3

  (399) 0x42ca58 LDR	X26, [SP, #184]

  (399) 0x42ca5c LDR	X27, [X27, #16]

  (399) 0x42ca60 LDR	X0, [SP, #208]

  (399) 0x42ca64 ADD	X17, X26, X17,LSL #3

  (399) 0x42ca68 STR	X27, [SP, #184]

  (399) 0x42ca6c LDP	X27, X26, [SP, #168]

  (399) 0x42ca70 LDR	X27, [X27, #16]

  (399) 0x42ca74 ADD	X26, X26, X0,LSL #3

  (399) 0x42ca78 LDR	X0, [SP, #216]

  (399) 0x42ca7c STR	X27, [SP, #176]

  (399) 0x42ca80 LDR	X27, [SP, #224]

  (399) 0x42ca84 ADD	X27, X27, X0,LSL #3

  (399) 0x42ca88 LDR	X0, [SP, #232]

  (399) 0x42ca8c ADD	X30, X0, X30,LSL #3

  (399) 0x42ca90 LDR	X0, [SP, #184]

  (399) 0x42ca94 ADD	X5, X0, X5,LSL #3

  (399) 0x42ca98 LDR	X0, [SP, #176]

  (399) 0x42ca9c ADD	X4, X0, X4,LSL #3

  (399) 0x42caa0 MOVZ	X0, #0

    (397) 0x42caa4 LD1D	{Z3.D}, P0/Z, [X18, X0,LSL #3]

    (397) 0x42caa8 LD1D	{Z6.D}, P0/Z, [X13, X0,LSL #3]

    (397) 0x42caac LD1D	{Z2.D}, P0/Z, [X11, X0,LSL #3]

    (397) 0x42cab0 LD1D	{Z17.D}, P0/Z, [X3, X0,LSL #3]

    (397) 0x42cab4 LD1D	{Z18.D}, P0/Z, [X16, X0,LSL #3]

    (397) 0x42cab8 LD1D	{Z20.D}, P0/Z, [X25, X0,LSL #3]

    (397) 0x42cabc LD1D	{Z22.D}, P0/Z, [X24, X0,LSL #3]

    (397) 0x42cac0 LD1D	{Z25.D}, P0/Z, [X20, X0,LSL #3]

    (397) 0x42cac4 LD1D	{Z26.D}, P0/Z, [X23, X0,LSL #3]

    (397) 0x42cac8 LD1D	{Z27.D}, P0/Z, [X14, X0,LSL #3]

    (397) 0x42cacc LD1D	{Z29.D}, P0/Z, [X22, X0,LSL #3]

    (397) 0x42cad0 LD1D	{Z31.D}, P0/Z, [X7, X0,LSL #3]

    (397) 0x42cad4 LD1D	{Z4.D}, P0/Z, [X21, X0,LSL #3]

    (397) 0x42cad8 LD1D	{Z1.D}, P0/Z, [X6, X0,LSL #3]

    (397) 0x42cadc FADD	Z7.D, Z6.D, Z3.D

    (397) 0x42cae0 FADD	Z19.D, Z17.D, Z2.D

    (397) 0x42cae4 LD1D	{Z6.D}, P0/Z, [X15, X0,LSL #3]

    (397) 0x42cae8 LD1D	{Z2.D}, P0/Z, [X10, X0,LSL #3]

    (397) 0x42caec FADD	Z21.D, Z19.D, Z7.D

    (397) 0x42caf0 FADD	Z24.D, Z22.D, Z20.D

    (397) 0x42caf4 FMUL	Z23.D, Z21.D, Z18.D

    (397) 0x42caf8 FADD	Z28.D, Z26.D, Z25.D

    (397) 0x42cafc FADD	Z0.D, Z31.D, Z29.D

    (397) 0x42cb00 FADD	Z3.D, Z1.D, Z4.D

    (397) 0x42cb04 FADD	Z30.D, Z28.D, Z24.D

    (397) 0x42cb08 FMAD	Z30.D, P1/M, Z27.D, Z23.D

    (397) 0x42cb0c LD1D	{Z31.D}, P0/Z, [X1, X0,LSL #3]

    (397) 0x42cb10 LD1D	{Z17.D}, P0/Z, [X9, X0,LSL #3]

    (397) 0x42cb14 LD1D	{Z20.D}, P0/Z, [X12, X0,LSL #3]

    (397) 0x42cb18 LD1D	{Z21.D}, P0/Z, [X8, X0,LSL #3]

    (397) 0x42cb1c LD1D	{Z22.D}, P0/Z, [X19, X0,LSL #3]

    (397) 0x42cb20 LD1D	{Z24.D}, P0/Z, [X17, X0,LSL #3]

    (397) 0x42cb24 LD1D	{Z26.D}, P0/Z, [X27, X0,LSL #3]

    (397) 0x42cb28 LD1D	{Z29.D}, P0/Z, [X26, X0,LSL #3]

    (397) 0x42cb2c FADD	Z7.D, Z3.D, Z0.D

    (397) 0x42cb30 FADD	Z19.D, Z17.D, Z6.D

    (397) 0x42cb34 LD1D	{Z0.D}, P0/Z, [X30, X0,LSL #3]

    (397) 0x42cb38 FMUL	Z18.D, Z7.D, Z2.D

    (397) 0x42cb3c MOVPRFX	Z4, Z5

    (397) 0x42cb40 FDIV	Z4.D, P1/M, Z4.D, Z31.D

    (397) 0x42cb44 FADD	Z23.D, Z21.D, Z20.D

    (397) 0x42cb48 FADD	Z27.D, Z26.D, Z24.D

    (397) 0x42cb4c FADD	Z25.D, Z23.D, Z19.D

    (397) 0x42cb50 FDIV	Z27.D, P1/M, Z27.D, Z29.D

    (397) 0x42cb54 FMAD	Z25.D, P1/M, Z22.D, Z18.D

    (397) 0x42cb58 FMUL	Z1.D, Z27.D, Z4.D

    (397) 0x42cb5c FSUB	Z28.D, Z25.D, Z30.D

    (397) 0x42cb60 FMUL	Z30.D, Z28.D, Z16.D

    (397) 0x42cb64 FADD	Z2.D, Z31.D, Z30.D

    (397) 0x42cb68 FMSB	Z30.D, P1/M, Z1.D, Z0.D

    (397) 0x42cb6c FDIV	Z31.D, P1/M, Z31.D, Z2.D

    (397) 0x42cb70 ST1D	{Z30.D}, P0, [X5, X0,LSL #3]

    (397) 0x42cb74 LD1D	{Z3.D}, P0/Z, [X26, X0,LSL #3]

    (397) 0x42cb78 FMUL	Z6.D, Z3.D, Z31.D

    (397) 0x42cb7c ST1D	{Z6.D}, P0, [X4, X0,LSL #3]

    (397) 0x42cb80 INCD	X0, ALL

    (397) 0x42cb84 WHILELO	P0.D, X0, X2

    (397) 0x42cb88 B.NE	42caa4

  (399) 0x42cb8c LDR	W24, [SP, #240]

  (399) 0x42cb90 ADD	X28, X28, #1

  (399) 0x42cb94 ADD	W2, W28, #0

  (399) 0x42cb98 CMP	W24, W2

  (399) 0x42cb9c B.LE	42cbe0

  (399) 0x42cba0 LDR	W8, [SP, #100]

  (399) 0x42cba4 LDR	W23, [SP, #252]

  (399) 0x42cba8 LDP	W9, W25, [SP, #244]

  (399) 0x42cbac SUB	W7, W23, W8

  (399) 0x42cbb0 CMP	W7, W25

  (399) 0x42cbb4 CSEL	W2, W7, W25, #9

  (399) 0x42cbb8 ADD	W23, W8, W2

  (399) 0x42cbbc STR	W23, [SP, #100]

  (399) 0x42cbc0 CMP	W8, W23

  (399) 0x42cbc4 B.CC	42c884

  (400) 0x42cbc8 LDR	W24, [SP, #240]

  (400) 0x42cbcc ADD	X28, X28, #1

  (400) 0x42cbd0 ADD	W2, W28, #0

  (400) 0x42cbd4 STR	W8, [SP, #100]

  (400) 0x42cbd8 CMP	W24, W2

  (400) 0x42cbdc B.GT	42cba0

(398) 0x42cbe0 LDP	X23, X24, [SP, #48]

(398) 0x42cbe4 LDP	X25, X26, [SP, #64]

(398) 0x42cbe8 LDP	X27, X28, [SP, #80]

(398) 0x42cbec LDP	X19, X20, [SP, #16]

(398) 0x42cbf0 LDP	X21, X22, [SP, #32]

(398) 0x42cbf4 LDP	X29, X30, [SP], #288

(398) 0x42cbf8 RET

  (396) 0x42cbfc LDP	X19, X20, [SP, #16]

  (396) 0x42cc00 LDP	X21, X22, [SP, #32]

  (396) 0x42cc04 LDP	X23, X24, [SP, #48]

  (396) 0x42cc08 LDP	X29, X30, [SP], #288

  (396) 0x42cc0c RET

  (396) 0x42cc10 ADD	W7, W7, #1

  (396) 0x42cc14 MOVZ	W8, #0

  (396) 0x42cc18 B	42c7b8

0x42cc1c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.62 cycles (7.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W1, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X20, #116]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W3, W4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42cbec <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W23, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42cbfc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W24, W23, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W5, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 42cc10 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W1, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X20, #116]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W3, W4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42cbec <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W23, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42cbfc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W24, W23, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W5, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 42cc10 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.13	0.95
▼Loop 398 - PdV.cpp:69-83 - exec–	0	0
▼Loop 399 - PdV.cpp:71-83 - exec–	0.04	0.01
○Loop 397 - PdV.cpp:72-83 - exec	4.09	0.94
○Loop 400 - PdV.cpp:71-83 - exec	0	0
○Loop 396 - PdV.cpp:69-71 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code