OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage: 4.09%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

0x42c360 STP	X29, X30, [SP, #832]!

0x42c364 ADD	X29, SP, #0

0x42c368 STP	X19, X20, [SP, #16]

0x42c36c ORR	X20, XZR, X0

0x42c370 STP	X23, X24, [SP, #48]

0x42c374 LDP	W23, W1, [X0, #104]

0x42c378 LDR	W0, [X0, #96]

0x42c37c LDR	W2, [X20, #100]

0x42c380 ADD	W3, W1, #2

0x42c384 ADD	W24, W23, #1

0x42c388 ADD	W4, W0, #1

0x42c38c STP	W3, W4, [SP, #160]

0x42c390 CMP	W24, W3

0x42c394 B.GE	42c70c

0x42c398 ADD	W19, W2, #2

0x42c39c STP	X21, X22, [SP, #32]

0x42c3a0 SUB	W22, W3, W24

0x42c3a4 CMP	W4, W19

0x42c3a8 B.GE	42c71c

0x42c3ac SUB	W5, W19, W4

0x42c3b0 MADD	W23, W22, W5, WZR

0x42c3b4 STR	W5, [SP, #168]

0x42c3b8 BL	403530

0x42c3bc ORR	W21, WZR, W0

0x42c3c0 BL	4033c0

0x42c3c4 UDIV	W7, W23, W21

0x42c3c8 ORR	W6, WZR, W0

0x42c3cc MSUB	W8, W7, W21, W23

0x42c3d0 CMP	W0, W8

0x42c3d4 B.CC	42c730

  (391) 0x42c3d8 MADD	W6, W7, W6, W8

  (391) 0x42c3dc ADD	W9, W7, W6

  (391) 0x42c3e0 STR	W9, [SP, #172]

  (391) 0x42c3e4 CMP	W6, W9

  (391) 0x42c3e8 B.CS	42c71c

(393) 0x42c3ec LDR	W10, [SP, #168]

(393) 0x42c3f0 FMOV	D0, #0.1250000

(393) 0x42c3f4 CNTD	X22, ALL

(393) 0x42c3f8 STP	X25, X26, [SP, #64]

(393) 0x42c3fc PTRUE	P0.B, ALL

(393) 0x42c400 FDUP	Z6.D, #112

(393) 0x42c404 LDR	W16, [SP, #164]

(393) 0x42c408 UDIV	W11, W6, W10

(393) 0x42c40c STP	X27, X28, [SP, #80]

(393) 0x42c410 LDR	X18, [X20, #56]

(393) 0x42c414 LDP	X28, X27, [X20, #8]

(393) 0x42c418 LDR	D5, [X20]

(393) 0x42c41c STR	X18, [SP, #136]

(393) 0x42c420 MSUB	W12, W11, W10, W6

(393) 0x42c424 LDR	X14, [X20, #24]

(393) 0x42c428 ADD	W13, W11, W24

(393) 0x42c42c SBFM	X3, X13, #0, #31

(393) 0x42c430 LDR	X17, [X20, #32]

(393) 0x42c434 ADD	W10, W12, W16

(393) 0x42c438 LDR	X25, [X20, #40]

(393) 0x42c43c SUB	W18, W19, W10

(393) 0x42c440 FMUL	D1, D5, D0

(393) 0x42c444 CMP	W7, W18

(393) 0x42c448 CSEL	W24, W7, W18, #9

(393) 0x42c44c STR	X14, [SP, #104]

(393) 0x42c450 LDR	X15, [X20, #48]

(393) 0x42c454 DUP	Z16.D, Z1.D[0]

(393) 0x42c458 STR	X17, [SP, #112]

(393) 0x42c45c LDR	X26, [X20, #64]

(393) 0x42c460 STR	X25, [SP, #144]

(393) 0x42c464 LDR	X30, [X20, #72]

(393) 0x42c468 STR	X15, [SP, #128]

(393) 0x42c46c LDR	X0, [X20, #80]

(393) 0x42c470 STR	X26, [SP, #184]

(393) 0x42c474 LDR	X20, [X20, #88]

(393) 0x42c478 STR	X30, [SP, #120]

(393) 0x42c47c ADD	W30, W6, W24

(393) 0x42c480 STR	X0, [SP, #176]

(393) 0x42c484 STR	X20, [SP, #96]

(393) 0x42c488 CMP	W6, W30

(393) 0x42c48c B.CS	42c6dc

  (394) 0x42c490 LDR	X4, [X27]

  (394) 0x42c494 SBFM	X1, X10, #0, #31

  (394) 0x42c498 ORR	W2, WZR, W24

  (394) 0x42c49c LDP	X21, X7, [SP, #96]

  (394) 0x42c4a0 ADD	X23, X1, #1

  (394) 0x42c4a4 WHILELO	P1.D, XZR, X2

  (394) 0x42c4a8 LDP	X13, X6, [SP, #176]

  (394) 0x42c4ac MADD	X19, X3, X4, XZR

  (394) 0x42c4b0 LDP	X11, X12, [SP, #112]

  (394) 0x42c4b4 ADD	X5, X4, X19

  (394) 0x42c4b8 ADD	X26, X19, X1

  (394) 0x42c4bc ORR	X9, XZR, X6

  (394) 0x42c4c0 ADD	X8, X5, X1

  (394) 0x42c4c4 LDP	X14, X15, [SP, #128]

  (394) 0x42c4c8 LDR	X10, [X21]

  (394) 0x42c4cc LDR	X19, [X13]

  (394) 0x42c4d0 LDR	X4, [X9]

  (394) 0x42c4d4 MADD	X16, X3, X10, XZR

  (394) 0x42c4d8 LDR	X9, [X28]

  (394) 0x42c4dc MADD	X5, X3, X19, XZR

  (394) 0x42c4e0 LDR	X25, [X7]

  (394) 0x42c4e4 ADD	X17, X10, X16

  (394) 0x42c4e8 ADD	X18, X16, X23

  (394) 0x42c4ec ADD	X20, X17, X1

  (394) 0x42c4f0 ADD	X24, X16, X1

  (394) 0x42c4f4 MADD	X16, X3, X4, X1

  (394) 0x42c4f8 ADD	X7, X19, X5

  (394) 0x42c4fc LDR	X11, [X11]

  (394) 0x42c500 ADD	X19, X5, X1

  (394) 0x42c504 MADD	X10, X3, X9, XZR

  (394) 0x42c508 ADD	X21, X7, X1

  (394) 0x42c50c ADD	X7, X7, X23

  (394) 0x42c510 LDR	X12, [X12]

  (394) 0x42c514 ADD	X9, X10, X1

  (394) 0x42c518 LDR	X0, [X6, #16]

  (394) 0x42c51c ADD	X6, X17, X23

  (394) 0x42c520 MADD	X17, X3, X25, X1

  (394) 0x42c524 ADD	X25, X5, X23

  (394) 0x42c528 ADD	X23, X10, X23

  (394) 0x42c52c LDR	X10, [SP, #96]

  (394) 0x42c530 MADD	X5, X3, X11, X1

  (394) 0x42c534 LDR	X4, [X15]

  (394) 0x42c538 MADD	X15, X3, X12, X1

  (394) 0x42c53c STR	X0, [SP, #152]

  (394) 0x42c540 LDR	X13, [X13, #16]

  (394) 0x42c544 LDR	X12, [X10, #16]

  (394) 0x42c548 MADD	X4, X3, X4, X1

  (394) 0x42c54c LDR	X11, [SP, #144]

  (394) 0x42c550 ADD	X21, X13, X21,LSL #3

  (394) 0x42c554 ADD	X7, X13, X7,LSL #3

  (394) 0x42c558 LDR	X14, [X14]

  (394) 0x42c55c ADD	X10, X12, X24,LSL #3

  (394) 0x42c560 ADD	X19, X13, X19,LSL #3

  (394) 0x42c564 LDR	X0, [SP, #112]

  (394) 0x42c568 ADD	X20, X12, X20,LSL #3

  (394) 0x42c56c LDR	X24, [X11]

  (394) 0x42c570 ADD	X11, X13, X25,LSL #3

  (394) 0x42c574 ADD	X6, X12, X6,LSL #3

  (394) 0x42c578 LDR	X25, [X27, #16]

  (394) 0x42c57c ADD	X18, X12, X18,LSL #3

  (394) 0x42c580 MADD	X14, X3, X14, X1

  (394) 0x42c584 MADD	X1, X3, X24, X1

  (394) 0x42c588 ADD	X13, X25, X26,LSL #3

  (394) 0x42c58c LDR	X26, [X28, #16]

  (394) 0x42c590 ADD	X8, X25, X8,LSL #3

  (394) 0x42c594 LDR	X25, [X0, #16]

  (394) 0x42c598 ADD	X12, X26, X23,LSL #3

  (394) 0x42c59c LDR	X23, [SP, #104]

  (394) 0x42c5a0 ADD	X9, X26, X9,LSL #3

  (394) 0x42c5a4 LDR	X26, [SP, #120]

  (394) 0x42c5a8 ADD	X5, X25, X5,LSL #3

  (394) 0x42c5ac LDR	X24, [X23, #16]

  (394) 0x42c5b0 LDR	X23, [X26, #16]

  (394) 0x42c5b4 LDR	X26, [SP, #136]

  (394) 0x42c5b8 ADD	X17, X24, X17,LSL #3

  (394) 0x42c5bc LDR	X24, [SP, #128]

  (394) 0x42c5c0 ADD	X15, X23, X15,LSL #3

  (394) 0x42c5c4 LDR	X0, [SP, #152]

  (394) 0x42c5c8 LDR	X23, [X26, #16]

  (394) 0x42c5cc LDR	X25, [X24, #16]

  (394) 0x42c5d0 ADD	X16, X0, X16,LSL #3

  (394) 0x42c5d4 LDR	X24, [SP, #144]

  (394) 0x42c5d8 ADD	X4, X23, X4,LSL #3

  (394) 0x42c5dc ADD	X14, X25, X14,LSL #3

  (394) 0x42c5e0 MOVZ	X25, #0

  (394) 0x42c5e4 LDR	X0, [X24, #16]

  (394) 0x42c5e8 ADD	X1, X0, X1,LSL #3

    (392) 0x42c5ec LD1D	{Z2.D}, P1/Z, [X13, X25,LSL #3]

    (392) 0x42c5f0 LD1D	{Z3.D}, P1/Z, [X10, X25,LSL #3]

    (392) 0x42c5f4 LD1D	{Z7.D}, P1/Z, [X18, X25,LSL #3]

    (392) 0x42c5f8 LD1D	{Z17.D}, P1/Z, [X9, X25,LSL #3]

    (392) 0x42c5fc LD1D	{Z21.D}, P1/Z, [X19, X25,LSL #3]

    (392) 0x42c600 LD1D	{Z22.D}, P1/Z, [X21, X25,LSL #3]

    (392) 0x42c604 LD1D	{Z23.D}, P1/Z, [X8, X25,LSL #3]

    (392) 0x42c608 FADD	Z18.D, Z7.D, Z3.D

    (392) 0x42c60c FADD	Z24.D, Z22.D, Z21.D

    (392) 0x42c610 FADD	Z4.D, Z2.D, Z2.D

    (392) 0x42c614 FADD	Z19.D, Z17.D, Z17.D

    (392) 0x42c618 FMUL	Z20.D, Z4.D, Z18.D

    (392) 0x42c61c FADD	Z25.D, Z23.D, Z23.D

    (392) 0x42c620 FMLA	Z20.D, P0/M, Z19.D, Z24.D

    (392) 0x42c624 LD1D	{Z26.D}, P1/Z, [X20, X25,LSL #3]

    (392) 0x42c628 LD1D	{Z19.D}, P1/Z, [X17, X25,LSL #3]

    (392) 0x42c62c LD1D	{Z27.D}, P1/Z, [X6, X25,LSL #3]

    (392) 0x42c630 LD1D	{Z28.D}, P1/Z, [X12, X25,LSL #3]

    (392) 0x42c634 LD1D	{Z0.D}, P1/Z, [X11, X25,LSL #3]

    (392) 0x42c638 LD1D	{Z5.D}, P1/Z, [X7, X25,LSL #3]

    (392) 0x42c63c LD1D	{Z2.D}, P1/Z, [X16, X25,LSL #3]

    (392) 0x42c640 LD1D	{Z1.D}, P1/Z, [X15, X25,LSL #3]

    (392) 0x42c644 LD1D	{Z7.D}, P1/Z, [X5, X25,LSL #3]

    (392) 0x42c648 MOVPRFX	Z21, Z6

    (392) 0x42c64c FDIV	Z21.D, P0/M, Z21.D, Z19.D

    (392) 0x42c650 FADD	Z29.D, Z27.D, Z26.D

    (392) 0x42c654 FADD	Z30.D, Z28.D, Z28.D

    (392) 0x42c658 FMUL	Z31.D, Z25.D, Z29.D

    (392) 0x42c65c FADD	Z3.D, Z5.D, Z0.D

    (392) 0x42c660 FADD	Z17.D, Z1.D, Z2.D

    (392) 0x42c664 FMAD	Z30.D, P0/M, Z3.D, Z31.D

    (392) 0x42c668 FDIV	Z17.D, P0/M, Z17.D, Z7.D

    (392) 0x42c66c FSUB	Z4.D, Z30.D, Z20.D

    (392) 0x42c670 FMUL	Z23.D, Z17.D, Z21.D

    (392) 0x42c674 LD1D	{Z20.D}, P1/Z, [X14, X25,LSL #3]

    (392) 0x42c678 FMUL	Z18.D, Z4.D, Z16.D

    (392) 0x42c67c FADD	Z22.D, Z19.D, Z18.D

    (392) 0x42c680 FMSB	Z18.D, P0/M, Z23.D, Z20.D

    (392) 0x42c684 FDIV	Z19.D, P0/M, Z19.D, Z22.D

    (392) 0x42c688 ST1D	{Z18.D}, P1, [X4, X25,LSL #3]

    (392) 0x42c68c LD1D	{Z24.D}, P1/Z, [X5, X25,LSL #3]

    (392) 0x42c690 FMUL	Z25.D, Z24.D, Z19.D

    (392) 0x42c694 ST1D	{Z25.D}, P1, [X1, X25,LSL #3]

    (392) 0x42c698 ADD	X25, X25, X22

    (392) 0x42c69c WHILELO	P1.D, X25, X2

    (392) 0x42c6a0 B.NE	42c5ec

  (394) 0x42c6a4 LDR	W20, [SP, #160]

  (394) 0x42c6a8 ADD	X3, X3, #1

  (394) 0x42c6ac ADD	W2, W3, #0

  (394) 0x42c6b0 CMP	W20, W2

  (394) 0x42c6b4 B.LE	42c700

  (394) 0x42c6b8 LDR	W21, [SP, #172]

  (394) 0x42c6bc ORR	W6, WZR, W30

  (394) 0x42c6c0 LDP	W10, W18, [SP, #164]

  (394) 0x42c6c4 SUB	W7, W21, W30

  (394) 0x42c6c8 CMP	W7, W18

  (394) 0x42c6cc CSEL	W24, W7, W18, #9

  (394) 0x42c6d0 ADD	W30, W6, W24

  (394) 0x42c6d4 CMP	W6, W30

  (394) 0x42c6d8 B.CC	42c490

  (395) 0x42c6dc LDR	W20, [SP, #160]

  (395) 0x42c6e0 ADD	X3, X3, #1

  (395) 0x42c6e4 ORR	W30, WZR, W6

  (395) 0x42c6e8 ADD	W2, W3, #0

  (395) 0x42c6ec CMP	W20, W2

  (395) 0x42c6f0 B.GT	42c6b8

(393) 0x42c6f4 HINT	#0

(393) 0x42c6f8 HINT	#0

(393) 0x42c6fc HINT	#0

(393) 0x42c700 LDP	X21, X22, [SP, #32]

(393) 0x42c704 LDP	X25, X26, [SP, #64]

(393) 0x42c708 LDP	X27, X28, [SP, #80]

(393) 0x42c70c LDP	X19, X20, [SP, #16]

(393) 0x42c710 LDP	X23, X24, [SP, #48]

(393) 0x42c714 LDP	X29, X30, [SP], #192

(393) 0x42c718 RET

  (391) 0x42c71c LDP	X19, X20, [SP, #16]

  (391) 0x42c720 LDP	X21, X22, [SP, #32]

  (391) 0x42c724 LDP	X23, X24, [SP, #48]

  (391) 0x42c728 LDP	X29, X30, [SP], #192

  (391) 0x42c72c RET

  (391) 0x42c730 ADD	W7, W7, #1

  (391) 0x42c734 MOVZ	W8, #0

  (391) 0x42c738 B	42c3d8

0x42c73c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:48-63

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.62 cycles (7.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W23, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X20, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W3, W4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42c70c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W22, W3, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42c71c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W23, W22, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W7, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W8, W7, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 42c730 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:48-63

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W23, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X20, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W3, W4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42c70c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W22, W3, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42c71c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W23, W22, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W7, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W8, W7, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 42c730 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.09	0.94
▼Loop 393 - PdV.cpp:48-63 - exec–	0	0
○Loop 395 - PdV.cpp:50-63 - exec	0	0
▼Loop 394 - PdV.cpp:50-63 - exec–	0	0
○Loop 392 - PdV.cpp:51-63 - exec	4.09	0.94
○Loop 391 - PdV.cpp:48-50 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code