OV - exec - Function ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: ideal_gas.cpp:37-45 [...]	Coverage: 6.64%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp: 37 - 45

--------------------------------------------------------------------------------

37: #pragma omp parallel for simd collapse(2)

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

0x427660 STP	X29, X30, [SP, #944]!

0x427664 ADD	X29, SP, #0

0x427668 STP	X19, X20, [SP, #16]

0x42766c STP	X25, X26, [SP, #64]

0x427670 LDP	W25, W19, [X0, #40]

0x427674 LDP	W20, W1, [X0, #32]

0x427678 ADD	W25, W25, #1

0x42767c ADD	W19, W19, #2

0x427680 CMP	W25, W19

0x427684 B.GE	427834

0x427688 ADD	W20, W20, #1

0x42768c STP	X21, X22, [SP, #32]

0x427690 ADD	W22, W1, #2

0x427694 SUB	W26, W19, W25

0x427698 CMP	W20, W22

0x42769c B.GE	427850

0x4276a0 SUB	W21, W22, W20

0x4276a4 STP	X23, X24, [SP, #48]

0x4276a8 ORR	X23, XZR, X0

0x4276ac MADD	W26, W26, W21, WZR

0x4276b0 BL	403530

0x4276b4 ORR	W24, WZR, W0

0x4276b8 BL	4033c0

0x4276bc UDIV	W3, W26, W24

0x4276c0 ORR	W2, WZR, W0

0x4276c4 MSUB	W0, W3, W24, W26

0x4276c8 CMP	W2, W0

0x4276cc B.CC	427844

(331) 0x4276d0 MADD	W2, W3, W2, W0

(331) 0x4276d4 ADD	W13, W3, W2

(331) 0x4276d8 CMP	W2, W13

(331) 0x4276dc B.CS	42782c

(331) 0x4276e0 UDIV	W4, W2, W21

(331) 0x4276e4 ADRP	X15,

(331) 0x4276e8 ADRP	X14,

(331) 0x4276ec ADD	X30, X15, #2304

(331) 0x4276f0 ADD	X26, X14, #2312

(331) 0x4276f4 FDUP	Z5.D, #112

(331) 0x4276f8 MOVZ	W16, #0

(331) 0x4276fc CNTD	X8, ALL

(331) 0x427700 PTRUE	P0.B, ALL

(331) 0x427704 LDP	X12, X11, [X23]

(331) 0x427708 LDP	X10, X9, [X23, #16]

(331) 0x42770c MSUB	W7, W4, W21, W2

(331) 0x427710 ADD	W5, W4, W25

(331) 0x427714 SBFM	X6, X5, #0, #31

(331) 0x427718 ADD	W4, W7, W20

(331) 0x42771c SUB	W17, W22, W4

(331) 0x427720 CMP	W3, W17

(331) 0x427724 CSEL	X1, X3, X17, #9

(331) 0x427728 ADD	W17, W2, W1

(331) 0x42772c CMP	W2, W17

(331) 0x427730 B.CS	427818

(331) 0x427734 HINT	#0

(331) 0x427738 HINT	#0

(331) 0x42773c HINT	#0

  (333) 0x427740 LDR	X22, [X10]

  (333) 0x427744 SBFM	X25, X4, #0, #31

  (333) 0x427748 MOVZ	X0, #0

  (333) 0x42774c LD1RD	{Z4.D}, P0/Z, [X30]

  (333) 0x427750 WHILELO	P1.D, XZR, X1

  (333) 0x427754 LD1RD	{Z3.D}, P0/Z, [X26]

  (333) 0x427758 LDR	X18, [X9]

  (333) 0x42775c LDR	X23, [X10, #16]

  (333) 0x427760 MADD	X2, X6, X22, X25

  (333) 0x427764 LDR	X4, [X11]

  (333) 0x427768 MADD	X24, X6, X18, X25

  (333) 0x42776c LDR	X7, [X12]

  (333) 0x427770 ADD	X3, X23, X2,LSL #3

  (333) 0x427774 LDR	X15, [X11, #16]

  (333) 0x427778 MADD	X14, X6, X4, X25

  (333) 0x42777c LDR	X18, [X12, #16]

  (333) 0x427780 MADD	X25, X6, X7, X25

  (333) 0x427784 LDR	X23, [X9, #16]

  (333) 0x427788 ADD	X5, X15, X14,LSL #3

  (333) 0x42778c ADD	X22, X18, X25,LSL #3

  (333) 0x427790 ADD	X24, X23, X24,LSL #3

  (333) 0x427794 HINT	#0

  (333) 0x427798 HINT	#0

  (333) 0x42779c HINT	#0

    (332) 0x4277a0 LD1D	{Z2.D}, P1/Z, [X22, X0,LSL #3]

    (332) 0x4277a4 LD1D	{Z1.D}, P1/Z, [X5, X0,LSL #3]

    (332) 0x4277a8 MOVPRFX	Z0, Z5

    (332) 0x4277ac FDIV	Z0.D, P0/M, Z0.D, Z2.D

    (332) 0x4277b0 FMUL	Z6.D, Z1.D, Z2.D

    (332) 0x4277b4 FMUL	Z7.D, Z0.D, Z0.D

    (332) 0x4277b8 FMUL	Z16.D, Z6.D, Z4.D

    (332) 0x4277bc ST1D	{Z16.D}, P1, [X3, X0,LSL #3]

    (332) 0x4277c0 LD1D	{Z17.D}, P1/Z, [X22, X0,LSL #3]

    (332) 0x4277c4 FMUL	Z18.D, Z17.D, Z3.D

    (332) 0x4277c8 FMUL	Z19.D, Z18.D, Z7.D

    (332) 0x4277cc FMUL	Z20.D, Z19.D, Z16.D

    (332) 0x4277d0 FSQRT	Z20.D, P0/M, Z20.D

    (332) 0x4277d4 ST1D	{Z20.D}, P1, [X24, X0,LSL #3]

    (332) 0x4277d8 ADD	X0, X0, X8

    (332) 0x4277dc WHILELO	P1.D, X0, X1

    (332) 0x4277e0 B.NE	4277a0

  (333) 0x4277e4 ADD	X6, X6, #1

  (333) 0x4277e8 ADD	W1, W16, W6

  (333) 0x4277ec CMP	W19, W1

  (333) 0x4277f0 B.LE	42782c

  (333) 0x4277f4 SUB	W3, W13, W17

  (333) 0x4277f8 ORR	W2, WZR, W17

  (333) 0x4277fc ORR	W17, WZR, W21

  (333) 0x427800 ORR	W4, WZR, W20

  (333) 0x427804 CMP	W3, W17

  (333) 0x427808 CSEL	X1, X3, X17, #9

  (333) 0x42780c ADD	W17, W2, W1

  (333) 0x427810 CMP	W2, W17

  (333) 0x427814 B.CC	427740

  (334) 0x427818 ADD	X6, X6, #1

  (334) 0x42781c ORR	W17, WZR, W2

  (334) 0x427820 ADD	W1, W16, W6

  (334) 0x427824 CMP	W19, W1

  (334) 0x427828 B.GT	4277f4

(331) 0x42782c LDP	X21, X22, [SP, #32]

(331) 0x427830 LDP	X23, X24, [SP, #48]

(331) 0x427834 LDP	X19, X20, [SP, #16]

(331) 0x427838 LDP	X25, X26, [SP, #64]

(331) 0x42783c LDP	X29, X30, [SP], #80

(331) 0x427840 RET

(331) 0x427844 ADD	W3, W3, #1

(331) 0x427848 MOVZ	W0, #0

(331) 0x42784c B	4276d0

0x427850 LDP	X21, X22, [SP, #32]

0x427854 B	427834

0x427858 HINT	#0

0x42785c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:37-45

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 427834 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 427850 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 427844 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 427834 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:37-45

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 427834 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 427850 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 427844 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 427834 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	6.64	1.52
▼Loop 331 - ideal_gas.cpp:37-45 - exec–	0	0
▼Loop 333 - ideal_gas.cpp:39-45 - exec–	0.04	0.01
○Loop 332 - ideal_gas.cpp:40-45 - exec	6.59	1.51
○Loop 334 - ideal_gas.cpp:39-45 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code