OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.1]	Module: exec	Source: generate_chunk.cpp:85-123 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 85 - 123

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

99:                 }

100:               }

101:             }

102:           }

103:         } else if (state_geometry[state] == g_circ) {

104:           double radius =

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

0x426d80 STP	X29, X30, [SP, #864]!

0x426d84 ADD	X29, SP, #0

0x426d88 STP	X19, X20, [SP, #16]

0x426d8c STP	X27, X28, [SP, #80]

0x426d90 LDP	W19, W27, [X0, #88]

0x426d94 CMP	W27, #0

0x426d98 B.LE	42704c

0x426d9c CMP	W19, #0

0x426da0 B.LE	42704c

0x426da4 ORR	X20, XZR, X0

0x426da8 STP	X21, X22, [SP, #32]

0x426dac MADD	W22, W27, W19, WZR

0x426db0 BL	403530

0x426db4 ORR	W21, WZR, W0

0x426db8 BL	4033c0

0x426dbc UDIV	W6, W22, W21

0x426dc0 ORR	W3, WZR, W0

0x426dc4 MSUB	W0, W6, W21, W22

0x426dc8 CMP	W3, W0

0x426dcc B.CC	42724c

0x426dd0 MADD	W3, W6, W3, W0

0x426dd4 ADD	W28, W6, W3

0x426dd8 CMP	W3, W28

0x426ddc B.CS	42705c

0x426de0 UDIV	W8, W3, W19

0x426de4 LDP	X7, X22, [X20]

0x426de8 STP	X23, X24, [SP, #48]

0x426dec LDRSW	X1, [X20, #96]

0x426df0 STR	X7, [SP, #128]

0x426df4 LDR	X10, [X20, #16]

0x426df8 STP	X25, X26, [SP, #64]

0x426dfc MSUB	W7, W8, W19, W3

0x426e00 SBFM	X9, X8, #0, #31

0x426e04 ADD	W8, W8, #1

0x426e08 UBFM	X2, X1, #62, #61

0x426e0c UBFM	X5, X1, #61, #60

0x426e10 LDR	X11, [X20, #24]

0x426e14 SUB	W13, W19, W7

0x426e18 STR	X2, [SP, #104]

0x426e1c LDR	X12, [X20, #56]

0x426e20 CMP	W6, W13

0x426e24 CSEL	W13, W6, W13, #9

0x426e28 STP	W19, W28, [SP, #112]

0x426e2c STR	X10, [SP, #136]

0x426e30 ADD	W10, W3, W13

0x426e34 STR	X11, [SP, #144]

0x426e38 LDP	X25, X21, [X20, #32]

0x426e3c STR	X12, [SP, #152]

0x426e40 LDR	X24, [X20, #48]

0x426e44 LDP	X30, X23, [X20, #64]

0x426e48 LDR	X4, [X20, #80]

0x426e4c CMP	W3, W10

0x426e50 B.CS	427024

0x426e54 HINT	#0

0x426e58 HINT	#0

0x426e5c HINT	#0

    (325) 0x426e60 SBFM	X1, X7, #0, #31

    (325) 0x426e64 SBFM	X15, X8, #0, #31

    (325) 0x426e68 LDR	X16, [X23, #8]

    (325) 0x426e6c SUB	W14, W13, #1

    (325) 0x426e70 ADD	X0, X1, #1

    (325) 0x426e74 UBFM	X13, X9, #61, #60

    (325) 0x426e78 ADD	X3, X0, X14

    (325) 0x426e7c STR	X15, [SP, #120]

    (325) 0x426e80 LDR	X17, [X25, #8]

    (325) 0x426e84 SBFM	X19, X8, #61, #31

    (325) 0x426e88 LDR	X26, [X24, #8]

    (325) 0x426e8c LDR	X18, [SP, #104]

    (325) 0x426e90 ADD	X7, X17, X5

    (325) 0x426e94 ADD	X6, X26, X5

    (325) 0x426e98 LDR	W2, [X16, X18]

    (325) 0x426e9c B	426ec0

    (325) 0x426ea0 CMP	W2, #2

    (325) 0x426ea4 B.EQ	427070

    (325) 0x426ea8 CMP	W2, #3

    (325) 0x426eac B.EQ	427168

    (325) 0x426eb0 ORR	X1, XZR, X0

    (325) 0x426eb4 CMP	X3, X0

    (325) 0x426eb8 B.EQ	426ff0

      (326) 0x426ebc ADD	X0, X0, #1

      (326) 0x426ec0 LDR	D3, [X6]

      (326) 0x426ec4 LDR	D1, [X7]

      (326) 0x426ec8 CMP	W2, #1

      (326) 0x426ecc B.NE	426ea0

      (326) 0x426ed0 LDR	X17, [X4, #600]

      (326) 0x426ed4 ADD	X16, X17, X1,LSL #3

      (326) 0x426ed8 LDR	D16, [X16, #8]

      (326) 0x426edc FCMPE	D16, D1

      (326) 0x426ee0 B.MI	426eb0

      (326) 0x426ee4 LDR	X15, [X21, #8]

      (326) 0x426ee8 LDR	D17, [X17, X1,LSL #3]

      (326) 0x426eec LDR	D18, [X15, X5]

      (326) 0x426ef0 FCMPE	D17, D18

      (326) 0x426ef4 B.GE	426eb0

      (326) 0x426ef8 LDR	X20, [X4, #632]

      (326) 0x426efc LDR	D19, [X20, X19]

      (326) 0x426f00 FCMPE	D19, D3

      (326) 0x426f04 B.MI	426eb0

      (326) 0x426f08 LDR	X18, [SP, #152]

      (326) 0x426f0c LDR	D20, [X20, X13]

      (326) 0x426f10 LDR	X28, [X18, #8]

      (326) 0x426f14 LDR	D21, [X28, X5]

      (326) 0x426f18 FCMPE	D20, D21

      (326) 0x426f1c B.GE	426eb0

      (326) 0x426f20 LDR	X11, [X22, #8]

      (326) 0x426f24 LDP	X28, X15, [SP, #120]

      (326) 0x426f28 LDR	X14, [X4, #48]

      (326) 0x426f2c LDR	D22, [X11, X5]

      (326) 0x426f30 LDR	X17, [X4]

      (326) 0x426f34 MADD	X12, X9, X14, X1

      (326) 0x426f38 LDR	X20, [X15, #8]

      (326) 0x426f3c LDR	X26, [X4, #64]

      (326) 0x426f40 MADD	X11, X9, X17, X1

      (326) 0x426f44 LDR	X16, [SP, #136]

      (326) 0x426f48 LDR	X14, [X4, #16]

      (326) 0x426f4c LDR	X15, [SP, #144]

      (326) 0x426f50 LDR	X17, [X16, #8]

      (326) 0x426f54 STR	D22, [X26, X12,LSL #3]

      (326) 0x426f58 LDR	D23, [X20, X5]

      (326) 0x426f5c LDR	X18, [X4, #168]

      (326) 0x426f60 LDR	X15, [X15, #8]

      (326) 0x426f64 LDR	X16, [X4, #184]

      (326) 0x426f68 STR	D23, [X14, X11,LSL #3]

      (326) 0x426f6c MADD	X26, X18, X9, XZR

      (326) 0x426f70 LDR	D24, [X17, X5]

      (326) 0x426f74 MADD	X12, X28, X18, XZR

      (326) 0x426f78 LDR	X11, [X4, #216]

      (326) 0x426f7c ADD	X18, X26, X1

      (326) 0x426f80 ADD	X20, X0, X26

      (326) 0x426f84 ADD	X26, X12, X1

      (326) 0x426f88 ADD	X12, X0, X12

      (326) 0x426f8c LDR	X14, [X4, #232]

      (326) 0x426f90 STR	D24, [X16, X18,LSL #3]

      (326) 0x426f94 LDR	D25, [X15, X5]

      (326) 0x426f98 MADD	X18, X11, X9, XZR

      (326) 0x426f9c MADD	X11, X28, X11, XZR

      (326) 0x426fa0 ADD	X28, X18, X1

      (326) 0x426fa4 ADD	X18, X0, X18

      (326) 0x426fa8 ADD	X1, X11, X1

      (326) 0x426fac ADD	X11, X0, X11

      (326) 0x426fb0 STR	D25, [X14, X28,LSL #3]

      (326) 0x426fb4 LDR	D26, [X17, X5]

      (326) 0x426fb8 STR	D26, [X16, X20,LSL #3]

      (326) 0x426fbc LDR	D27, [X15, X5]

      (326) 0x426fc0 STR	D27, [X14, X18,LSL #3]

      (326) 0x426fc4 LDR	D28, [X17, X5]

      (326) 0x426fc8 STR	D28, [X16, X26,LSL #3]

      (326) 0x426fcc LDR	D29, [X15, X5]

      (326) 0x426fd0 STR	D29, [X14, X1,LSL #3]

      (326) 0x426fd4 ORR	X1, XZR, X0

      (326) 0x426fd8 LDR	D30, [X17, X5]

      (326) 0x426fdc STR	D30, [X16, X12,LSL #3]

      (326) 0x426fe0 LDR	D31, [X15, X5]

      (326) 0x426fe4 STR	D31, [X14, X11,LSL #3]

      (326) 0x426fe8 CMP	X3, X0

      (326) 0x426fec B.NE	426ebc

      (327) 0x426ff0 ADD	X9, X9, #1

      (327) 0x426ff4 CMP	W27, W8

      (327) 0x426ff8 B.LE	427040

      (328) 0x426ffc LDP	W13, W0, [SP, #112]

      (328) 0x427000 ORR	W3, WZR, W10

      (328) 0x427004 MOVZ	W7, #0

      (328) 0x427008 ADD	W8, W8, #1

      (328) 0x42700c SUB	W6, W0, W10

      (328) 0x427010 CMP	W6, W13

      (328) 0x427014 CSEL	W13, W6, W13, #9

      (328) 0x427018 ADD	W10, W3, W13

      (328) 0x42701c CMP	W3, W10

      (328) 0x427020 B.CC	426e60

      (328) 0x427024 ORR	W10, WZR, W3

      (328) 0x427028 ADD	X9, X9, #1

      (328) 0x42702c CMP	W27, W8

      (328) 0x427030 B.GT	426ffc

(323) 0x427034 HINT	#0

(323) 0x427038 HINT	#0

(323) 0x42703c HINT	#0

(323) 0x427040 LDP	X21, X22, [SP, #32]

(323) 0x427044 LDP	X23, X24, [SP, #48]

(323) 0x427048 LDP	X25, X26, [SP, #64]

(323) 0x42704c LDP	X19, X20, [SP, #16]

(323) 0x427050 LDP	X27, X28, [SP, #80]

(323) 0x427054 LDP	X29, X30, [SP], #160

(323) 0x427058 RET

(323) 0x42705c LDP	X19, X20, [SP, #16]

(323) 0x427060 LDP	X21, X22, [SP, #32]

(323) 0x427064 LDP	X27, X28, [SP, #80]

(323) 0x427068 LDP	X29, X30, [SP], #160

(323) 0x42706c RET

  (324) 0x427070 LDR	X16, [X4, #568]

  (324) 0x427074 LDR	X17, [X4, #536]

  (324) 0x427078 LDR	X15, [X30, #8]

  (324) 0x42707c LDR	D22, [X16, X13]

  (324) 0x427080 LDR	D23, [X17, X1,LSL #3]

  (324) 0x427084 LDR	D29, [X15, X5]

  (324) 0x427088 FSUB	D24, D22, S3

  (324) 0x42708c FSUB	D25, D23, S1

  (324) 0x427090 FMUL	D26, D24, D24

  (324) 0x427094 FMADD	D27, D25, D25, D26

  (324) 0x427098 FSQRT	D28, D27

  (324) 0x42709c FCMPE	D29, D28

  (324) 0x4270a0 B.MI	426eb0

  (324) 0x4270a4 LDR	X11, [X22, #8]

  (324) 0x4270a8 LDP	X28, X17, [SP, #128]

  (324) 0x4270ac LDR	X18, [X4, #48]

  (324) 0x4270b0 LDR	D30, [X11, X5]

  (324) 0x4270b4 LDR	X16, [X28, #8]

  (324) 0x4270b8 MADD	X12, X9, X18, X1

  (324) 0x4270bc LDR	X26, [X4, #64]

  (324) 0x4270c0 LDR	X14, [X4]

  (324) 0x4270c4 LDR	X17, [X17, #8]

  (324) 0x4270c8 STR	D30, [X26, X12,LSL #3]

  (324) 0x4270cc LDR	D31, [X16, X5]

  (324) 0x4270d0 MADD	X20, X9, X14, X1

  (324) 0x4270d4 LDR	X12, [X4, #168]

  (324) 0x4270d8 LDR	X18, [X4, #16]

  (324) 0x4270dc LDR	X15, [SP, #144]

  (324) 0x4270e0 MADD	X11, X12, X9, XZR

  (324) 0x4270e4 LDR	X16, [X4, #184]

  (324) 0x4270e8 ADD	X14, X12, X11

  (324) 0x4270ec ADD	X26, X1, X11

  (324) 0x4270f0 LDR	X15, [X15, #8]

  (324) 0x4270f4 ADD	X28, X0, X14

  (324) 0x4270f8 STR	D31, [X18, X20,LSL #3]

  (324) 0x4270fc ADD	X20, X0, X11

  (324) 0x427100 ADD	X18, X1, X14

  (324) 0x427104 LDR	D3, [X17, X5]

  (324) 0x427108 LDR	X11, [X4, #216]

  (324) 0x42710c LDR	X14, [X4, #232]

  (324) 0x427110 STR	D3, [X16, X26,LSL #3]

  (324) 0x427114 LDR	D1, [X15, X5]

  (324) 0x427118 MADD	X12, X11, X9, XZR

  (324) 0x42711c ADD	X26, X1, X12

  (324) 0x427120 ADD	X11, X11, X12

  (324) 0x427124 ADD	X12, X0, X12

  (324) 0x427128 ADD	X1, X1, X11

  (324) 0x42712c STR	D1, [X14, X26,LSL #3]

  (324) 0x427130 ADD	X26, X0, X11

  (324) 0x427134 LDR	D0, [X17, X5]

  (324) 0x427138 STR	D0, [X16, X20,LSL #3]

  (324) 0x42713c LDR	D2, [X15, X5]

  (324) 0x427140 STR	D2, [X14, X12,LSL #3]

  (324) 0x427144 LDR	D4, [X17, X5]

  (324) 0x427148 STR	D4, [X16, X18,LSL #3]

  (324) 0x42714c LDR	D5, [X15, X5]

  (324) 0x427150 STR	D5, [X14, X1,LSL #3]

  (324) 0x427154 LDR	D6, [X17, X5]

  (324) 0x427158 STR	D6, [X16, X28,LSL #3]

  (324) 0x42715c LDR	D7, [X15, X5]

  (324) 0x427160 STR	D7, [X14, X26,LSL #3]

  (324) 0x427164 B	426eb0

    (325) 0x427168 LDR	X20, [X4, #600]

    (325) 0x42716c LDR	D0, [X20, X1,LSL #3]

    (325) 0x427170 FCMP	D0, D1

    (325) 0x427174 B.NE	426eb0

    (325) 0x427178 LDR	X28, [X4, #632]

    (325) 0x42717c LDR	D2, [X28, X13]

    (325) 0x427180 FCMP	D2, D3

    (325) 0x427184 B.NE	426eb0

    (325) 0x427188 LDR	X14, [X22, #8]

    (325) 0x42718c LDP	X17, X26, [SP, #128]

    (325) 0x427190 LDR	X11, [X4, #48]

    (325) 0x427194 LDR	D4, [X14, X5]

    (325) 0x427198 LDR	X20, [X17, #8]

    (325) 0x42719c MADD	X12, X9, X11, X1

    (325) 0x4271a0 LDR	X15, [X4, #64]

    (325) 0x4271a4 LDR	X16, [X4]

    (325) 0x4271a8 LDR	X17, [X26, #8]

    (325) 0x4271ac STR	D4, [X15, X12,LSL #3]

    (325) 0x4271b0 LDR	D5, [X20, X5]

    (325) 0x4271b4 MADD	X18, X9, X16, X1

    (325) 0x4271b8 LDR	X12, [X4, #168]

    (325) 0x4271bc LDR	X28, [X4, #16]

    (325) 0x4271c0 LDR	X11, [SP, #144]

    (325) 0x4271c4 MADD	X14, X12, X9, XZR

    (325) 0x4271c8 LDR	X16, [X4, #184]

    (325) 0x4271cc ADD	X20, X14, X1

    (325) 0x4271d0 LDR	X15, [X11, #8]

    (325) 0x4271d4 STR	D5, [X28, X18,LSL #3]

    (325) 0x4271d8 ADD	X28, X14, X12

    (325) 0x4271dc ADD	X18, X14, X0

    (325) 0x4271e0 LDR	D6, [X17, X5]

    (325) 0x4271e4 ADD	X26, X28, X1

    (325) 0x4271e8 ADD	X11, X28, X0

    (325) 0x4271ec LDR	X12, [X4, #216]

    (325) 0x4271f0 LDR	X14, [X4, #232]

    (325) 0x4271f4 STR	D6, [X16, X20,LSL #3]

    (325) 0x4271f8 LDR	D7, [X15, X5]

    (325) 0x4271fc MADD	X20, X12, X9, XZR

    (325) 0x427200 ADD	X28, X20, X1

    (325) 0x427204 ADD	X12, X12, X20

    (325) 0x427208 ADD	X20, X20, X0

    (325) 0x42720c ADD	X1, X12, X1

    (325) 0x427210 STR	D7, [X14, X28,LSL #3]

    (325) 0x427214 ADD	X28, X12, X0

    (325) 0x427218 LDR	D16, [X17, X5]

    (325) 0x42721c STR	D16, [X16, X18,LSL #3]

    (325) 0x427220 LDR	D17, [X15, X5]

    (325) 0x427224 STR	D17, [X14, X20,LSL #3]

    (325) 0x427228 LDR	D18, [X17, X5]

    (325) 0x42722c STR	D18, [X16, X26,LSL #3]

    (325) 0x427230 LDR	D19, [X15, X5]

    (325) 0x427234 STR	D19, [X14, X1,LSL #3]

    (325) 0x427238 LDR	D20, [X17, X5]

    (325) 0x42723c STR	D20, [X16, X11,LSL #3]

    (325) 0x427240 LDR	D21, [X15, X5]

    (325) 0x427244 STR	D21, [X14, X28,LSL #3]

    (325) 0x427248 B	426eb0

0x42724c ADD	W6, W6, #1

0x427250 MOVZ	W0, #0

0x427254 B	426dd0

0x427258 HINT	#0

0x42725c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:85-123

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.33 to 0.94 cycles (7.82x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.33 to 1.00 cycles (7.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 100 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	7.33	7.33	7.33	6.00	6.00
cycles	4.00	4.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	7.33	7.33	7.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	7.00
Overall L1	7.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles. At this rate:

14% of peak load performance is reached (13.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (19.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W19, W27, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42704c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42704c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD W22, W27, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W6, W22, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W0, W6, W21, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 42724c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W3, W6, W3, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W28, W6, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 42705c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W8, W3, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDP X7, X22, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRSW X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W7, W8, W19, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X9, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W19, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W6, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W13, W6, W13, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W19, W28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W10, W3, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X21, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X24, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X23, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W3, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 427024 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426dd0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:85-123

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.33 to 1.00 cycles (7.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 100 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	7.33	7.33	7.33	6.00	6.00
cycles	4.00	4.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	7.33	7.33	7.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	7.00
Overall L1	7.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles. At this rate:

14% of peak load performance is reached (13.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (19.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W19, W27, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42704c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42704c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD W22, W27, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W6, W22, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W0, W6, W21, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 42724c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W3, W6, W3, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W28, W6, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 42705c <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W8, W3, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDP X7, X22, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRSW X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W7, W8, W19, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X9, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W19, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W6, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W13, W6, W13, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W19, W28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W10, W3, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X21, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X24, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X23, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W3, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 427024 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426dd0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.1]–	0.02	0
▼Loop 323 - generate_chunk.cpp:85-123 - exec–	0	0
▼Loop 324 - generate_chunk.cpp:85-123 - exec–	0	0
▼Loop 325 - generate_chunk.cpp:85-123 - exec–	0	0
○Loop 326 - generate_chunk.cpp:88-116 - exec	0.02	0
○Loop 328 - generate_chunk.cpp:85-95 - exec	0	0
○Loop 327 - generate_chunk.cpp:95-95 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code