OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0]	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 74 - 80

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

0x426be0 STP	X29, X30, [SP, #960]!

0x426be4 ADD	X29, SP, #0

0x426be8 STP	X19, X20, [SP, #16]

0x426bec LDP	W19, W20, [X0, #40]

0x426bf0 CMP	W20, #0

0x426bf4 B.LE	426d68

0x426bf8 CMP	W19, #0

0x426bfc B.LE	426d68

0x426c00 STP	X21, X22, [SP, #32]

0x426c04 ORR	X22, XZR, X0

0x426c08 STR	X23, [SP, #48]

0x426c0c MADD	W23, W20, W19, WZR

0x426c10 BL	403530

0x426c14 ORR	W21, WZR, W0

0x426c18 BL	4033c0

0x426c1c UDIV	W1, W23, W21

0x426c20 ORR	W2, WZR, W0

0x426c24 MSUB	W3, W1, W21, W23

0x426c28 CMP	W0, W3

0x426c2c B.CC	426d74

(319) 0x426c30 MADD	W3, W1, W2, W3

(319) 0x426c34 ADD	W11, W1, W3

(319) 0x426c38 CMP	W3, W11

(319) 0x426c3c B.CS	426d60

(319) 0x426c40 UDIV	W6, W3, W19

(319) 0x426c44 LDP	X16, X15, [X22]

(319) 0x426c48 MOVZ	W12, #0

(319) 0x426c4c CNTD	X9, ALL

(319) 0x426c50 PTRUE	P1.B, ALL

(319) 0x426c54 LDP	X14, X13, [X22, #16]

(319) 0x426c58 LDR	X7, [X22, #32]

(319) 0x426c5c MSUB	W21, W6, W19, W3

(319) 0x426c60 SBFM	X6, X6, #0, #31

(319) 0x426c64 SUB	W10, W19, W21

(319) 0x426c68 CMP	W1, W10

(319) 0x426c6c CSEL	W22, W1, W10, #9

(319) 0x426c70 ADD	W10, W3, W22

(319) 0x426c74 CMP	W3, W10

(319) 0x426c78 B.CS	426d40

(319) 0x426c7c HINT	#0

  (321) 0x426c80 SBFM	X8, X21, #0, #31

  (321) 0x426c84 LDR	X5, [X7]

  (321) 0x426c88 MOVZ	X0, #0

  (321) 0x426c8c WHILELO	P0.D, WZR, W22

  (321) 0x426c90 LDR	X4, [X7, #48]

  (321) 0x426c94 LDR	X21, [X7, #168]

  (321) 0x426c98 MADD	X23, X6, X5, X8

  (321) 0x426c9c LDR	X2, [X7, #216]

  (321) 0x426ca0 MADD	X1, X6, X4, X8

  (321) 0x426ca4 LDR	X30, [X7, #16]

  (321) 0x426ca8 MADD	X3, X6, X21, X8

  (321) 0x426cac LDR	X18, [X7, #64]

  (321) 0x426cb0 MADD	X21, X6, X2, X8

  (321) 0x426cb4 LDR	X17, [X7, #184]

  (321) 0x426cb8 ADD	X5, X30, X23,LSL #3

  (321) 0x426cbc LDR	X8, [X7, #232]

  (321) 0x426cc0 ADD	X4, X18, X1,LSL #3

  (321) 0x426cc4 LDR	X30, [X15, #8]

  (321) 0x426cc8 ADD	X23, X17, X3,LSL #3

  (321) 0x426ccc LDR	X1, [X13, #8]

  (321) 0x426cd0 ADD	X2, X8, X21,LSL #3

  (321) 0x426cd4 LDR	X17, [X14, #8]

  (321) 0x426cd8 LDR	X18, [X16, #8]

  (321) 0x426cdc HINT	#0

    (320) 0x426ce0 LD1RD	{Z0.D}, P1/Z, [X30]

    (320) 0x426ce4 ST1D	{Z0.D}, P0, [X4, X0,LSL #3]

    (320) 0x426ce8 LD1RD	{Z1.D}, P1/Z, [X18]

    (320) 0x426cec ST1D	{Z1.D}, P0, [X5, X0,LSL #3]

    (320) 0x426cf0 LD1RD	{Z2.D}, P1/Z, [X17]

    (320) 0x426cf4 ST1D	{Z2.D}, P0, [X23, X0,LSL #3]

    (320) 0x426cf8 LD1RD	{Z3.D}, P1/Z, [X1]

    (320) 0x426cfc ST1D	{Z3.D}, P0, [X2, X0,LSL #3]

    (320) 0x426d00 ADD	X0, X0, X9

    (320) 0x426d04 WHILELO	P0.D, W0, W22

    (320) 0x426d08 B.NE	426ce0

  (321) 0x426d0c ADD	X6, X6, #1

  (321) 0x426d10 ADD	W22, W12, W6

  (321) 0x426d14 CMP	W20, W22

  (321) 0x426d18 B.LE	426d60

  (321) 0x426d1c SUB	W1, W11, W10

  (321) 0x426d20 ORR	W3, WZR, W10

  (321) 0x426d24 ORR	W10, WZR, W19

  (321) 0x426d28 MOVZ	W21, #0

  (321) 0x426d2c CMP	W1, W10

  (321) 0x426d30 CSEL	W22, W1, W10, #9

  (321) 0x426d34 ADD	W10, W3, W22

  (321) 0x426d38 CMP	W3, W10

  (321) 0x426d3c B.CC	426c80

  (322) 0x426d40 ADD	X6, X6, #1

  (322) 0x426d44 ORR	W10, WZR, W3

  (322) 0x426d48 ADD	W22, W12, W6

  (322) 0x426d4c CMP	W20, W22

  (322) 0x426d50 B.GT	426d1c

(319) 0x426d54 HINT	#0

(319) 0x426d58 HINT	#0

(319) 0x426d5c HINT	#0

(319) 0x426d60 LDP	X21, X22, [SP, #32]

(319) 0x426d64 LDR	X23, [SP, #48]

(319) 0x426d68 LDP	X19, X20, [SP, #16]

(319) 0x426d6c LDP	X29, X30, [SP], #64

(319) 0x426d70 RET

(319) 0x426d74 ADD	W1, W1, #1

(319) 0x426d78 MOVZ	W3, #0

(319) 0x426d7c B	426c30

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.25 to 0.47 cycles (6.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00
cycles	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.50
Overall L1	3.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.25 cycles. At this rate:

2% of peak load performance is reached (2.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426be0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W19, W20, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 426d68 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 426d68 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD W23, W20, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W3, W1, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 426d74 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00
cycles	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	2.00	2.00	1.00	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.50
Overall L1	3.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.25 cycles. At this rate:

2% of peak load performance is reached (2.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426be0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W19, W20, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 426d68 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 426d68 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD W23, W20, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W3, W1, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 426d74 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0]–	0.04	0.01
▼Loop 319 - generate_chunk.cpp:74-80 - exec–	0	0
○Loop 322 - generate_chunk.cpp:74-80 - exec	0	0
▼Loop 321 - generate_chunk.cpp:74-80 - exec–	0	0
○Loop 320 - generate_chunk.cpp:77-80 - exec	0.04	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code