OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage: 2.2%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

0x426760 STP	X29, X30, [SP, #912]!

0x426764 ADD	X29, SP, #0

0x426768 STP	X19, X20, [SP, #16]

0x42676c STP	X21, X22, [SP, #32]

0x426770 LDP	W22, W19, [X0, #80]

0x426774 STP	X27, X28, [SP, #80]

0x426778 ORR	X28, XZR, X0

0x42677c LDR	W0, [X0, #72]

0x426780 ADD	W27, W22, #1

0x426784 ADD	W19, W19, #3

0x426788 LDR	W2, [X28, #76]

0x42678c ADD	W1, W0, #1

0x426790 STR	W1, [SP, #104]

0x426794 CMP	W27, W19

0x426798 B.GE	4269d4

0x42679c ADD	W20, W2, #3

0x4267a0 STP	X23, X24, [SP, #48]

0x4267a4 SUB	W23, W19, W27

0x4267a8 CMP	W1, W20

0x4267ac B.GE	4269e8

0x4267b0 SUB	W3, W20, W1

0x4267b4 MADD	W24, W23, W3, WZR

0x4267b8 STR	W3, [SP, #108]

0x4267bc BL	403530

0x4267c0 ORR	W21, WZR, W0

0x4267c4 BL	4033c0

0x4267c8 UDIV	W4, W24, W21

0x4267cc ORR	W5, WZR, W0

0x4267d0 MSUB	W6, W4, W21, W24

0x4267d4 CMP	W0, W6

0x4267d8 B.CC	426a00

  (312) 0x4267dc MADD	W6, W4, W5, W6

  (312) 0x4267e0 ADD	W30, W4, W6

  (312) 0x4267e4 CMP	W6, W30

  (312) 0x4267e8 B.CS	4269e8

(314) 0x4267ec LDR	W7, [SP, #108]

(314) 0x4267f0 FMOV	D0, #0.2500000

(314) 0x4267f4 CNTD	X15, ALL

(314) 0x4267f8 STP	X25, X26, [SP, #64]

(314) 0x4267fc LDR	W11, [SP, #104]

(314) 0x426800 UDIV	W8, W6, W7

(314) 0x426804 LDP	X25, X24, [X28, #24]

(314) 0x426808 LDP	X23, X22, [X28, #40]

(314) 0x42680c LDR	D3, [X28]

(314) 0x426810 MSUB	W9, W8, W7, W6

(314) 0x426814 ADD	W10, W8, W27

(314) 0x426818 LDP	X27, X26, [X28, #8]

(314) 0x42681c SBFM	X8, X10, #0, #31

(314) 0x426820 ADD	W13, W9, W11

(314) 0x426824 FMUL	D1, D3, D0

(314) 0x426828 DUP	Z5.D, Z1.D[0]

(314) 0x42682c SUB	W18, W20, W13

(314) 0x426830 LDP	X21, X20, [X28, #56]

(314) 0x426834 ORR	W28, WZR, W30

(314) 0x426838 CMP	W4, W18

(314) 0x42683c CSEL	W12, W4, W18, #9

(314) 0x426840 ADD	W18, W6, W12

(314) 0x426844 CMP	W6, W18

(314) 0x426848 B.CS	4269b8

  (315) 0x42684c SBFM	X1, X13, #0, #31

  (315) 0x426850 ORR	W2, WZR, W12

  (315) 0x426854 WHILELO	P0.D, XZR, X2

  (315) 0x426858 LDR	X5, [X23]

  (315) 0x42685c ADD	X14, X1, #1

  (315) 0x426860 MOVZ	X0, #0

  (315) 0x426864 LDR	X13, [X21]

  (315) 0x426868 LDR	X4, [X23, #16]

  (315) 0x42686c MADD	X30, X5, X8, XZR

  (315) 0x426870 LDR	X16, [X22]

  (315) 0x426874 MADD	X3, X8, X13, X1

  (315) 0x426878 LDR	X10, [X24]

  (315) 0x42687c ADD	X7, X30, X1

  (315) 0x426880 ADD	X6, X5, X30

  (315) 0x426884 ADD	X13, X4, X7,LSL #3

  (315) 0x426888 ADD	X9, X6, X1

  (315) 0x42688c LDR	X7, [X25]

  (315) 0x426890 ADD	X6, X4, X9,LSL #3

  (315) 0x426894 MADD	X17, X8, X16, XZR

  (315) 0x426898 LDR	X12, [X20]

  (315) 0x42689c MADD	X11, X8, X10, XZR

  (315) 0x4268a0 ADD	X9, X17, X14

  (315) 0x4268a4 ADD	X4, X17, X1

  (315) 0x4268a8 LDR	X16, [X21, #16]

  (315) 0x4268ac MADD	X17, X8, X7, XZR

  (315) 0x4268b0 ADD	X30, X11, X14

  (315) 0x4268b4 LDR	X14, [X25, #16]

  (315) 0x4268b8 ADD	X5, X11, X1

  (315) 0x4268bc ADD	X10, X7, X17

  (315) 0x4268c0 ADD	X11, X17, X1

  (315) 0x4268c4 LDR	X17, [X26]

  (315) 0x4268c8 ADD	X7, X10, X1

  (315) 0x4268cc STR	X16, [SP, #96]

  (315) 0x4268d0 LDR	X16, [X22, #16]

  (315) 0x4268d4 ADD	X7, X14, X7,LSL #3

  (315) 0x4268d8 ADD	X14, X14, X11,LSL #3

  (315) 0x4268dc LDR	X11, [X27]

  (315) 0x4268e0 MADD	X10, X8, X17, X1

  (315) 0x4268e4 LDR	X17, [X27, #16]

  (315) 0x4268e8 ADD	X9, X16, X9,LSL #3

  (315) 0x4268ec MADD	X11, X8, X11, X1

  (315) 0x4268f0 MADD	X1, X8, X12, X1

  (315) 0x4268f4 LDR	X12, [X20, #16]

  (315) 0x4268f8 ADD	X11, X17, X11,LSL #3

  (315) 0x4268fc ADD	X17, X12, X1,LSL #3

  (315) 0x426900 LDR	X1, [X24, #16]

  (315) 0x426904 ADD	X12, X1, X30,LSL #3

  (315) 0x426908 LDR	X30, [X22, #16]

  (315) 0x42690c ADD	X5, X1, X5,LSL #3

  (315) 0x426910 LDR	X1, [X26, #16]

  (315) 0x426914 ADD	X4, X30, X4,LSL #3

  (315) 0x426918 LDR	X30, [SP, #96]

  (315) 0x42691c ADD	X10, X1, X10,LSL #3

  (315) 0x426920 ADD	X3, X30, X3,LSL #3

    (313) 0x426924 LD1D	{Z6.D}, P0/Z, [X14, X0,LSL #3]

    (313) 0x426928 LD1D	{Z2.D}, P0/Z, [X7, X0,LSL #3]

    (313) 0x42692c LD1D	{Z4.D}, P0/Z, [X13, X0,LSL #3]

    (313) 0x426930 LD1D	{Z16.D}, P0/Z, [X6, X0,LSL #3]

    (313) 0x426934 LD1D	{Z17.D}, P0/Z, [X11, X0,LSL #3]

    (313) 0x426938 FADD	Z7.D, Z2.D, Z6.D

    (313) 0x42693c FADD	Z18.D, Z16.D, Z4.D

    (313) 0x426940 FMUL	Z19.D, Z5.D, Z17.D

    (313) 0x426944 FADD	Z20.D, Z18.D, Z7.D

    (313) 0x426948 FMUL	Z21.D, Z20.D, Z19.D

    (313) 0x42694c ST1D	{Z21.D}, P0, [X3, X0,LSL #3]

    (313) 0x426950 LD1D	{Z22.D}, P0/Z, [X5, X0,LSL #3]

    (313) 0x426954 LD1D	{Z23.D}, P0/Z, [X12, X0,LSL #3]

    (313) 0x426958 LD1D	{Z24.D}, P0/Z, [X4, X0,LSL #3]

    (313) 0x42695c LD1D	{Z26.D}, P0/Z, [X9, X0,LSL #3]

    (313) 0x426960 LD1D	{Z27.D}, P0/Z, [X10, X0,LSL #3]

    (313) 0x426964 FADD	Z25.D, Z23.D, Z22.D

    (313) 0x426968 FADD	Z28.D, Z26.D, Z24.D

    (313) 0x42696c FMUL	Z29.D, Z27.D, Z5.D

    (313) 0x426970 FADD	Z30.D, Z28.D, Z25.D

    (313) 0x426974 FMUL	Z31.D, Z30.D, Z29.D

    (313) 0x426978 ST1D	{Z31.D}, P0, [X17, X0,LSL #3]

    (313) 0x42697c ADD	X0, X0, X15

    (313) 0x426980 WHILELO	P0.D, X0, X2

    (313) 0x426984 B.NE	426924

  (315) 0x426988 ADD	X8, X8, #1

  (315) 0x42698c ADD	W2, W8, #0

  (315) 0x426990 CMP	W19, W2

  (315) 0x426994 B.LE	4269cc

  (315) 0x426998 SUB	W4, W28, W18

  (315) 0x42699c ORR	W6, WZR, W18

  (315) 0x4269a0 LDP	W13, W18, [SP, #104]

  (315) 0x4269a4 CMP	W4, W18

  (315) 0x4269a8 CSEL	W12, W4, W18, #9

  (315) 0x4269ac ADD	W18, W6, W12

  (315) 0x4269b0 CMP	W6, W18

  (315) 0x4269b4 B.CC	42684c

  (316) 0x4269b8 ADD	X8, X8, #1

  (316) 0x4269bc ORR	W18, WZR, W6

  (316) 0x4269c0 ADD	W2, W8, #0

  (316) 0x4269c4 CMP	W19, W2

  (316) 0x4269c8 B.GT	426998

(314) 0x4269cc LDP	X23, X24, [SP, #48]

(314) 0x4269d0 LDP	X25, X26, [SP, #64]

(314) 0x4269d4 LDP	X19, X20, [SP, #16]

(314) 0x4269d8 LDP	X21, X22, [SP, #32]

(314) 0x4269dc LDP	X27, X28, [SP, #80]

(314) 0x4269e0 LDP	X29, X30, [SP], #112

(314) 0x4269e4 RET

  (312) 0x4269e8 LDP	X19, X20, [SP, #16]

  (312) 0x4269ec LDP	X21, X22, [SP, #32]

  (312) 0x4269f0 LDP	X23, X24, [SP, #48]

  (312) 0x4269f4 LDP	X27, X28, [SP, #80]

  (312) 0x4269f8 LDP	X29, X30, [SP], #112

  (312) 0x4269fc RET

  (312) 0x426a00 ADD	W4, W4, #1

  (312) 0x426a04 MOVZ	W6, #0

  (312) 0x426a08 B	4267dc

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.62 cycles (7.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.88
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W19, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W27, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X28, #76]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W27, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4269d4 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W23, W19, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W1, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4269e8 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W3, W20, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W24, W23, W3, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR W3, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W4, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W6, W4, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 426a00 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.88
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W19, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W27, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X28, #76]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W27, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4269d4 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W23, W19, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W1, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4269e8 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W3, W20, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W24, W23, W3, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR W3, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W4, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W6, W4, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 426a00 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	2.2	0.5
▼Loop 314 - flux_calc.cpp:36-40 - exec–	0	0
▼Loop 315 - flux_calc.cpp:38-40 - exec–	0.02	0
○Loop 313 - flux_calc.cpp:39-40 - exec	2.18	0.5
○Loop 316 - flux_calc.cpp:38-40 - exec	0	0
○Loop 312 - flux_calc.cpp:36-38 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code