OV - exec - Function field_summary(global_variables&, parallel_&) [clone ._omp

	Function: field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]	Module: exec	Source: field_summary.cpp:75-91 [...]	Coverage: 0.7%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp: 75 - 91

--------------------------------------------------------------------------------

75: #pragma omp parallel for simd reduction(+ : press) reduction(+ : ke) reduction(+ : ie) reduction(+ : mass) reduction(+ : vol)

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

0x426300 STP	X29, X30, [SP, #896]!

0x426304 ADD	X29, SP, #0

0x426308 STP	X19, X20, [SP, #16]

0x42630c STP	X21, X22, [SP, #32]

0x426310 ORR	X21, XZR, X0

0x426314 STP	X23, X24, [SP, #48]

0x426318 LDP	W19, W24, [X0, #48]

0x42631c STP	D8, D9, [SP, #96]

0x426320 LDR	W0, [X0, #56]

0x426324 STP	D10, D11, [SP, #112]

0x426328 LDR	W23, [X21, #60]

0x42632c SUB	W1, W19, W24

0x426330 STR	D12, [SP, #88]

0x426334 ADD	W2, W1, #1

0x426338 SUB	W3, W0, W23

0x42633c ADD	W22, W3, #1

0x426340 MADD	W19, W3, W2, W2

0x426344 BL	403530

0x426348 ORR	W20, WZR, W0

0x42634c BL	4033c0

0x426350 SDIV	W4, W19, W20

0x426354 MSUB	W5, W4, W20, W19

0x426358 CMP	W0, W5

0x42635c B.LT	42651c

0x426360 MADD	W5, W4, W0, W5

0x426364 ADD	W7, W4, W5

0x426368 CMP	W5, W7

0x42636c B.GE	426504

0x426370 MOVI	D8, #0

0x426374 LDR	X12, [X21]

0x426378 FMOV	D17, #0.1250000

0x42637c ADD	W10, W23, #1

0x426380 ADD	W11, W24, #1

0x426384 STP	X25, X26, [SP, #64]

0x426388 FMOV	D12, D8

0x42638c FMOV	D11, D8

0x426390 FMOV	D10, D8

0x426394 FMOV	D9, D8

0x426398 LDR	X19, [X12]

0x42639c LDR	X18, [X12, #16]

0x4263a0 LDR	X17, [X12, #48]

0x4263a4 LDR	X16, [X12, #64]

0x4263a8 LDR	X15, [X12, #96]

0x4263ac LDR	X14, [X12, #112]

0x4263b0 LDR	X9, [X12, #168]

0x4263b4 LDR	X6, [X12, #184]

0x4263b8 LDR	X8, [X12, #216]

0x4263bc LDR	X0, [X12, #232]

0x4263c0 LDR	X13, [X12, #656]

0x4263c4 LDR	X12, [X12, #672]

0x4263c8 STR	X27, [SP, #80]

(308) 0x4263cc SDIV	W25, W5, W22

(308) 0x4263d0 ADD	W26, W25, W11

(308) 0x4263d4 MSUB	W27, W25, W22, W5

(308) 0x4263d8 ADD	W5, W5, #1

(308) 0x4263dc SBFM	X3, X26, #0, #31

(308) 0x4263e0 ADD	W30, W26, #1

(308) 0x4263e4 SBFM	X24, X30, #0, #31

(308) 0x4263e8 MADD	X2, X8, X3, XZR

(308) 0x4263ec ADD	W1, W27, W10

(308) 0x4263f0 SBFM	X20, X1, #0, #31

(308) 0x4263f4 MADD	X23, X9, X3, XZR

(308) 0x4263f8 ADD	W4, W1, #1

(308) 0x4263fc SBFM	X27, X4, #0, #31

(308) 0x426400 MADD	X30, X9, X24, XZR

(308) 0x426404 ADD	X25, X20, X2

(308) 0x426408 ADD	X4, X2, X27

(308) 0x42640c MADD	X2, X8, X24, XZR

(308) 0x426410 ADD	X26, X20, X23

(308) 0x426414 ADD	X23, X23, X27

(308) 0x426418 MADD	X24, X13, X3, X20

(308) 0x42641c LDR	D2, [X0, X25,LSL #3]

(308) 0x426420 ADD	X25, X20, X30

(308) 0x426424 ADD	X30, X27, X30

(308) 0x426428 ADD	X1, X27, X2

(308) 0x42642c ADD	X2, X20, X2

(308) 0x426430 MADD	X27, X19, X3, X20

(308) 0x426434 LDR	D0, [X6, X26,LSL #3]

(308) 0x426438 MADD	X26, X17, X3, X20

(308) 0x42643c MADD	X3, X15, X3, X20

(308) 0x426440 LDR	D1, [X6, X23,LSL #3]

(308) 0x426444 FMUL	D6, D2, D2

(308) 0x426448 LDR	D5, [X0, X4,LSL #3]

(308) 0x42644c LDR	D4, [X6, X25,LSL #3]

(308) 0x426450 LDR	D3, [X0, X2,LSL #3]

(308) 0x426454 FMADD	D16, D0, D0, D6

(308) 0x426458 LDR	D7, [X12, X24,LSL #3]

(308) 0x42645c LDR	D18, [X18, X27,LSL #3]

(308) 0x426460 FMADD	D19, D1, D1, D16

(308) 0x426464 LDR	D20, [X6, X30,LSL #3]

(308) 0x426468 LDR	D21, [X0, X1,LSL #3]

(308) 0x42646c FADD	D8, D8, D7

(308) 0x426470 FMUL	D22, D7, D18

(308) 0x426474 LDR	D23, [X16, X26,LSL #3]

(308) 0x426478 FMADD	D24, D5, D5, D19

(308) 0x42647c LDR	D25, [X14, X3,LSL #3]

(308) 0x426480 FMADD	D26, D4, D4, D24

(308) 0x426484 FMUL	D27, D22, D17

(308) 0x426488 FMADD	D11, D22, D23, D11

(308) 0x42648c FADD	D12, D12, D22

(308) 0x426490 FMADD	D9, D7, D25, D9

(308) 0x426494 FMADD	D28, D3, D3, D26

(308) 0x426498 FMADD	D29, D20, D20, D28

(308) 0x42649c FMADD	D30, D21, D21, D29

(308) 0x4264a0 FMADD	D10, D27, D30, D10

(308) 0x4264a4 CMP	W7, W5

(308) 0x4264a8 B.NE	4263cc

0x4264ac LDP	X25, X26, [SP, #64]

0x4264b0 LDR	X27, [SP, #80]

0x4264b4 BL	4034e0

0x4264b8 LDP	D31, D17, [X21, #8]

0x4264bc LDP	X19, X20, [SP, #16]

0x4264c0 LDP	X23, X24, [SP, #48]

0x4264c4 FADD	D6, D31, D8

0x4264c8 FADD	D5, D17, D12

0x4264cc LDP	D2, D1, [X21, #24]

0x4264d0 LDR	D0, [X21, #40]

0x4264d4 LDR	D12, [SP, #88]

0x4264d8 FADD	D4, D2, D11

0x4264dc FADD	D3, D1, D10

0x4264e0 LDP	D10, D11, [SP, #112]

0x4264e4 FADD	D16, D0, D9

0x4264e8 LDP	D8, D9, [SP, #96]

0x4264ec STP	D6, D5, [X21, #8]

0x4264f0 STP	D4, D3, [X21, #24]

0x4264f4 STR	D16, [X21, #40]

0x4264f8 LDP	X21, X22, [SP, #32]

0x4264fc LDP	X29, X30, [SP], #128

0x426500 B	4033f0

0x426504 MOVI	D8, #0

0x426508 FMOV	D12, D8

0x42650c FMOV	D11, D8

0x426510 FMOV	D10, D8

0x426514 FMOV	D9, D8

0x426518 B	4264b4

0x42651c ADD	W4, W4, #1

0x426520 MOVZ	W5, #0

0x426524 B	426360

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	field_summary.cpp:75-91
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp:75-91

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 4.00 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.33 to 2.83 cycles (4.71x speedup).

Details

27% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.33 to 1.50 cycles (8.89x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 288 bytes. The binary function is storing 168 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	82
loop length	328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	5.50	5.50	5.50	5.50	5.50	5.50	5.50	5.50	13.33	13.33	13.33	3.00	3.00
cycles	4.00	4.00	5.50	5.50	5.50	5.50	5.50	5.50	5.50	5.50	13.33	13.33	13.33	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.25
Overall L1	13.33

Vectorization ratios

all	27%
load	66%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

22% of peak load performance is reached (21.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W19, W24, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W0, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W23, [X21, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W1, W19, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D12, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W2, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W3, W0, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W19, W3, W2, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV W4, W19, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W5, W4, W20, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42651c <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W5, W4, W0, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W7, W4, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426504 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D17, #0.1250000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W10, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X12, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X12, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X12, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X12, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X12, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4034e0 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D31, D17, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FADD D6, D31, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D5, D17, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D2, D1, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D4, D2, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D1, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STP D6, D5, [X21, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D4, D3, [X21, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D16, [X21, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4033f0 <@plt_start@+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 4264b4 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426360 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	field_summary.cpp:75-91
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp:75-91

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 4.00 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

27% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.33 to 1.50 cycles (8.89x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 288 bytes. The binary function is storing 168 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	82
loop length	328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	5.50	5.50	5.50	5.50	5.50	5.50	5.50	5.50	13.33	13.33	13.33	3.00	3.00
cycles	4.00	4.00	5.50	5.50	5.50	5.50	5.50	5.50	5.50	5.50	13.33	13.33	13.33	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.25
Overall L1	13.33

Vectorization ratios

all	27%
load	66%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

22% of peak load performance is reached (21.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W19, W24, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W0, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W23, [X21, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W1, W19, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D12, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W2, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W3, W0, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W19, W3, W2, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV W4, W19, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W5, W4, W20, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42651c <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W5, W4, W0, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W7, W4, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426504 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D17, #0.1250000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W10, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X12, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X12, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X12, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X12, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X12, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4034e0 <@plt_start@+0x460>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D31, D17, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FADD D6, D31, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D5, D17, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D2, D1, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D4, D2, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D1, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STP D6, D5, [X21, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D4, D3, [X21, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D16, [X21, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4033f0 <@plt_start@+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 4264b4 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426360 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]–	0.7	0.16
○Loop 308 - context.h:69-69 - exec	0.7	0.16

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code