OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75	Coverage: 10.27%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

0x424400 STP	X29, X30, [SP, #864]!

0x424404 ADD	X29, SP, #0

0x424408 STP	X19, X20, [SP, #16]

0x42440c ORR	X19, XZR, X0

0x424410 STP	X21, X22, [SP, #32]

0x424414 LDP	W22, W2, [X0, #128]

0x424418 STP	D8, D9, [SP, #96]

0x42441c LDR	W0, [X0, #120]

0x424420 STP	D10, D11, [SP, #112]

0x424424 LDR	W1, [X19, #124]

0x424428 ADD	W3, W2, #2

0x42442c ADD	W22, W22, #1

0x424430 LDP	D8, D11, [X19]

0x424434 ADD	W4, W0, #1

0x424438 STR	W3, [SP, #152]

0x42443c LDP	D10, D9, [X19, #16]

0x424440 STR	W4, [SP, #128]

0x424444 CMP	W22, W3

0x424448 B.GE	4247b8

0x42444c LDR	W6, [SP, #152]

0x424450 ADD	W21, W1, #2

0x424454 STP	X23, X24, [SP, #48]

0x424458 LDR	W7, [SP, #128]

0x42445c SUB	W24, W6, W22

0x424460 CMP	W7, W21

0x424464 B.GE	4246fc

0x424468 SUB	W20, W21, W7

0x42446c BL	403530

0x424470 MADD	W24, W24, W20, WZR

0x424474 ORR	W23, WZR, W0

0x424478 BL	4033c0

0x42447c UDIV	W8, W24, W23

0x424480 MSUB	W9, W8, W23, W24

0x424484 CMP	W0, W9

0x424488 B.CC	4247a4

0x42448c MADD	W7, W8, W0, W9

0x424490 ADD	W10, W8, W7

0x424494 STR	W10, [SP, #156]

0x424498 CMP	W7, W10

0x42449c B.CS	4246fc

0x4244a0 UDIV	W12, W7, W20

0x4244a4 LDR	W18, [SP, #128]

0x4244a8 MOVN	X13, #32784

0x4244ac ADRP	X14,

0x4244b0 ADRP	X16,

0x4244b4 STP	X27, X28, [SP, #80]

0x4244b8 FADD	D6, D11, D11

0x4244bc FADD	D5, D10, D10

0x4244c0 ADRP	X15,

0x4244c4 FMOV	D16, #0.5000000

0x4244c8 FMOV	D18, #-1.0000000

0x4244cc FMOV	D1, X13

0x4244d0 LDP	X0, X27, [X19, #48]

0x4244d4 STP	X25, X26, [SP, #64]

0x4244d8 MSUB	W17, W12, W20, W7

0x4244dc ADD	W28, W12, W22

0x4244e0 LDR	D4, [X14, #2368]

0x4244e4 SBFM	X4, X28, #0, #31

0x4244e8 LDP	X26, X25, [X19, #32]

0x4244ec SUB	W1, W28, W4

0x4244f0 ADD	W2, W17, W18

0x4244f4 SUB	W12, W21, W2

0x4244f8 LDP	X24, X23, [X19, #64]

0x4244fc LDP	X30, X18, [X19, #96]

0x424500 STR	X0, [SP, #136]

0x424504 ORR	X0, XZR, X4

0x424508 LDR	D3, [X16, #4088]

0x42450c STR	W1, [SP, #132]

0x424510 LDR	X22, [X19, #80]

0x424514 LDR	X21, [X19, #88]

0x424518 LDR	D7, [X15, #2264]

0x42451c ADD	X15, X4, #1

  (295) 0x424520 CMP	W8, W12

  (295) 0x424524 CSEL	W5, W8, W12, #9

  (295) 0x424528 ADD	W17, W7, W5

  (295) 0x42452c CMP	W7, W17

  (295) 0x424530 B.CS	424758

  (296) 0x424534 LDR	X28, [X23]

  (296) 0x424538 SUB	W6, W5, #1

  (296) 0x42453c SBFM	X3, X2, #0, #31

  (296) 0x424540 ADD	X4, X3, #1

  (296) 0x424544 ADD	W2, W2, #1

  (296) 0x424548 LDR	X8, [X18]

  (296) 0x42454c ADD	X7, X6, X4

  (296) 0x424550 SBFM	X1, X2, #0, #31

  (296) 0x424554 LDR	X9, [X21]

  (296) 0x424558 MADD	X6, X0, X28, XZR

  (296) 0x42455c STR	X1, [SP, #144]

  (296) 0x424560 LDR	X12, [X22]

  (296) 0x424564 UBFM	X2, X8, #61, #60

  (296) 0x424568 LDR	X5, [X23, #16]

  (296) 0x42456c MADD	X11, X0, X9, XZR

  (296) 0x424570 LDR	X8, [X24]

  (296) 0x424574 MADD	X13, X0, X12, XZR

  (296) 0x424578 LDR	X10, [X21, #16]

  (296) 0x42457c ADD	X12, X5, X6,LSL #3

  (296) 0x424580 LDR	X16, [X22, #16]

  (296) 0x424584 LDR	X5, [X26]

  (296) 0x424588 ADD	X14, X10, X11,LSL #3

  (296) 0x42458c LDR	X9, [X24, #16]

  (296) 0x424590 MADD	X10, X0, X8, XZR

  (296) 0x424594 ADD	X13, X16, X13,LSL #3

  (296) 0x424598 LDR	X16, [X25]

  (296) 0x42459c MADD	X6, X0, X5, XZR

  (296) 0x4245a0 LDR	X8, [X26, #16]

  (296) 0x4245a4 ADD	X11, X9, X10,LSL #3

  (296) 0x4245a8 LDR	X9, [X30]

  (296) 0x4245ac UBFM	X10, X16, #61, #60

  (296) 0x4245b0 LDR	X28, [X25, #16]

  (296) 0x4245b4 ADD	X6, X8, X6,LSL #3

  (296) 0x4245b8 LDR	X16, [X18, #16]

  (296) 0x4245bc UBFM	X5, X9, #61, #60

  (296) 0x4245c0 LDR	X8, [X30, #16]

  (296) 0x4245c4 LDR	X1, [X27, #8]

  (296) 0x4245c8 MADD	X9, X0, X5, X8

  (296) 0x4245cc MADD	X5, X15, X5, X8

  (296) 0x4245d0 MADD	X8, X0, X2, X16

  (296) 0x4245d4 LDR	D17, [X1, X0,LSL #3]

  (296) 0x4245d8 MADD	X2, X15, X2, X16

  (296) 0x4245dc MADD	X16, X10, X0, X28

  (296) 0x4245e0 LDR	X1, [SP, #144]

  (296) 0x4245e4 MADD	X10, X15, X10, X28

  (296) 0x4245e8 LDR	X28, [SP, #136]

  (296) 0x4245ec LDR	X28, [X28, #8]

  (296) 0x4245f0 FMINNM	D22, D1, D3

  (296) 0x4245f4 LDR	D20, [X2, X3,LSL #3]

  (296) 0x4245f8 LDR	D2, [X9, X1,LSL #3]

  (296) 0x4245fc LDR	D0, [X5, X1,LSL #3]

  (296) 0x424600 LDR	D1, [X2, X1,LSL #3]

  (296) 0x424604 LDR	D24, [X10, X3,LSL #3]

  (296) 0x424608 FADD	D21, D2, D0

  (296) 0x42460c LDR	D27, [X9, X3,LSL #3]

  (296) 0x424610 FADD	D26, D20, D1

  (296) 0x424614 LDR	D19, [X5, X3,LSL #3]

  (296) 0x424618 LDR	D23, [X6, X1,LSL #3]

  (296) 0x42461c LDR	D25, [X6, X3,LSL #3]

  (296) 0x424620 FMUL	D29, D26, D24

  (296) 0x424624 FADD	D31, D27, D19

  (296) 0x424628 LDR	D30, [X8, X3,LSL #3]

  (296) 0x42462c FMUL	D28, D21, D23

  (296) 0x424630 LDR	D11, [X8, X1,LSL #3]

  (296) 0x424634 LDR	D21, [X16, X3,LSL #3]

  (296) 0x424638 FMUL	D1, D31, D25

  (296) 0x42463c LDR	D2, [X13, X3,LSL #3]

  (296) 0x424640 FABS	D26, D29

  (296) 0x424644 FADD	D23, D28, D29

  (296) 0x424648 FADD	D0, D30, D11

  (296) 0x42464c LDR	D24, [X11, X3,LSL #3]

  (296) 0x424650 FABS	D10, D28

  (296) 0x424654 LDR	D28, [X12, X3,LSL #3]

  (296) 0x424658 FADD	D30, D2, D2

  (296) 0x42465c LDR	D27, [X28, X3,LSL #3]

  (296) 0x424660 FMINNM	D25, D17, D27

  (296) 0x424664 FMUL	D11, D25, D8

  (296) 0x424668 FSUB	D19, D23, S1

  (296) 0x42466c FMUL	D31, D0, D21

  (296) 0x424670 LDR	D20, [X14, X3,LSL #3]

  (296) 0x424674 FMUL	D27, D24, D4

  (296) 0x424678 FMUL	D23, D6, D24

  (296) 0x42467c ORR	X3, XZR, X4

  (296) 0x424680 FMUL	D29, D5, D24

  (296) 0x424684 FABS	D21, D1

  (296) 0x424688 FMAXNM	D10, D21, D10

  (296) 0x42468c FMAXNM	D1, D10, D27

  (296) 0x424690 FDIV	D28, D30, D28

  (296) 0x424694 FSUB	D2, D19, S31

  (296) 0x424698 FABS	D0, D31

  (296) 0x42469c FMAXNM	D26, D0, D26

  (296) 0x4246a0 FMAXNM	D30, D26, D27

  (296) 0x4246a4 FDIV	D19, D23, D1

  (296) 0x4246a8 FMUL	D31, D2, D16

  (296) 0x4246ac FDIV	D25, D29, D30

  (296) 0x4246b0 FMINNM	D21, D19, D25

  (296) 0x4246b4 FMINNM	D22, D22, D21

  (296) 0x4246b8 FMADD	D20, D20, D20, D28

  (296) 0x4246bc FDIV	D24, D31, D24

  (296) 0x4246c0 FSQRT	D23, D20

  (296) 0x4246c4 FMAXNM	D10, D23, D4

  (296) 0x4246c8 FDIV	D11, D11, D10

  (296) 0x4246cc FMINNM	D27, D11, D3

  (296) 0x4246d0 FCMPE	D24, D7

  (296) 0x4246d4 B.GE	424744

  (297) 0x4246d8 FDIV	D28, D18, D24

  (297) 0x4246dc ADD	X1, X1, #1

  (297) 0x4246e0 FMUL	D2, D28, D9

  (297) 0x4246e4 FMINNM	D0, D2, D11

  (297) 0x4246e8 FMINNM	D1, D0, D22

  (297) 0x4246ec CMP	X4, X7

  (297) 0x4246f0 B.EQ	424754

  (297) 0x4246f4 ADD	X4, X4, #1

  (297) 0x4246f8 B	4245f0

0x4246fc MOVN	X11, #32784

0x424700 LDP	X23, X24, [SP, #48]

0x424704 FMOV	D4, X11

(294) 0x424708 ADD	X19, X19, #112

(294) 0x42470c LDR	X1, [X19]

  (292) 0x424710 FMOV	D5, X1

  (292) 0x424714 ORR	X22, XZR, X1

  (292) 0x424718 FMINNM	D6, D4, D5

  (292) 0x42471c FMOV	X30, D6

  (292) 0x424720 CASAL	X22, X30, [X19]

  (292) 0x424724 CMP	X1, X22

  (292) 0x424728 B.NE	4247b0

(294) 0x42472c LDP	X19, X20, [SP, #16]

(294) 0x424730 LDP	X21, X22, [SP, #32]

(294) 0x424734 LDP	D8, D9, [SP, #96]

(294) 0x424738 LDP	D10, D11, [SP, #112]

(294) 0x42473c LDP	X29, X30, [SP], #160

(294) 0x424740 RET

  (293) 0x424744 ADD	X1, X1, #1

  (293) 0x424748 FMINNM	D1, D22, D27

  (293) 0x42474c CMP	X4, X7

  (293) 0x424750 B.NE	4246f4

(294) 0x424754 ORR	W7, WZR, W17

  (295) 0x424758 LDR	W14, [SP, #132]

  (295) 0x42475c ADD	X0, X0, #1

  (295) 0x424760 ADD	X15, X15, #1

  (295) 0x424764 LDR	W17, [SP, #152]

  (295) 0x424768 ADD	W4, W14, W0

  (295) 0x42476c CMP	W17, W4

  (295) 0x424770 B.LE	424788

  (295) 0x424774 LDR	W11, [SP, #156]

  (295) 0x424778 ORR	W12, WZR, W20

  (295) 0x42477c LDR	W2, [SP, #128]

  (295) 0x424780 SUB	W8, W11, W7

  (295) 0x424784 B	424520

(294) 0x424788 MOVN	X20, #32784

(294) 0x42478c LDP	X23, X24, [SP, #48]

(294) 0x424790 FMOV	D3, X20

(294) 0x424794 FMINNM	D4, D1, D3

(294) 0x424798 LDP	X25, X26, [SP, #64]

(294) 0x42479c LDP	X27, X28, [SP, #80]

(294) 0x4247a0 B	424708

0x4247a4 ADD	W8, W8, #1

0x4247a8 MOVZ	W9, #0

0x4247ac B	42448c

  (292) 0x4247b0 ORR	X1, XZR, X22

  (292) 0x4247b4 B	424710

0x4247b8 MOVN	X5, #32784

0x4247bc FMOV	D4, X5

0x4247c0 B	424708

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:49-75.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 2.33 cycles (4.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 10.50 to 1.94 cycles (5.42x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.50 to 1.00 cycles (10.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 180 bytes. The binary function is storing 152 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	81
loop length	324
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	10.50	10.17	10.33	5.50	5.50
cycles	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	10.50	10.17	10.33	5.50	5.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	10.13
Overall L1	10.50

Vectorization ratios

all	12%
load	40%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W2, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W0, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W1, [X19, #124]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D8, D11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP D10, D9, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4247b8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W21, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W24, W6, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4246fc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W24, W24, W20, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W8, W24, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W9, W8, W23, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4247a4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W8, W0, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W10, W8, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W10, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W7, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4246fc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W12, W7, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR W18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X13, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X14, <4424ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X16, <4424b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FADD D6, D11, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D5, D10, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADRP X15, <4434c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D16, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D18, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, X13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X0, X27, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W17, W12, W20, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W28, W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X14, #2368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SBFM X4, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X26, X25, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB W1, W28, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X24, X23, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X18, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X16, #4088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W1, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D7, [X15, #2264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X15, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X11, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D4, X11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42448c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVN X5, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D4, X5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 424708 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:49-75.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 2.33 cycles (4.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.50 to 1.00 cycles (10.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 180 bytes. The binary function is storing 152 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	81
loop length	324
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	10.50	10.17	10.33	5.50	5.50
cycles	4.00	4.00	9.50	9.50	9.50	9.50	2.25	2.25	2.25	2.25	10.50	10.17	10.33	5.50	5.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	10.13
Overall L1	10.50

Vectorization ratios

all	12%
load	40%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W2, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W0, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W1, [X19, #124]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D8, D11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP D10, D9, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4247b8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W21, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W24, W6, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4246fc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W24, W24, W20, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W8, W24, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W9, W8, W23, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4247a4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W8, W0, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W10, W8, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W10, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W7, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4246fc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W12, W7, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR W18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X13, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X14, <4424ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X16, <4424b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FADD D6, D11, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D5, D10, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADRP X15, <4434c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D16, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D18, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, X13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X0, X27, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W17, W12, W20, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W28, W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X14, #2368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SBFM X4, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X26, X25, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB W1, W28, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X24, X23, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X18, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X16, #4088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W1, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D7, [X15, #2264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X15, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X11, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D4, X11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42448c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVN X5, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D4, X5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 424708 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	10.27	2.36
▼Loop 294 - calc_dt.cpp:49-75 - exec–	0	0
○Loop 293 - calc_dt.cpp:49-75 - exec	6.79	1.56
○Loop 296 - calc_dt.cpp:52-75 - exec	3.29	0.75
○Loop 297 - calc_dt.cpp:70-75 - exec	0.17	0.04
○Loop 295 - calc_dt.cpp:51-69 - exec	0.02	0
○Loop 292 - calc_dt.cpp:49-49 - exec	0	0

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code