OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage: 9.25%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

[...]

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x421d24 STP	X29, X30, [SP, #912]!

0x421d28 ADD	X29, SP, #0

0x421d2c STP	X19, X20, [SP, #16]

0x421d30 LDR	W19, [X0, #52]

0x421d34 STP	X23, X24, [SP, #48]

0x421d38 ORR	X23, XZR, X0

0x421d3c STP	X25, X26, [SP, #64]

0x421d40 ADD	W19, W19, #3

0x421d44 LDR	W26, [X23, #48]

0x421d48 LDR	W20, [X0, #40]

0x421d4c LDR	W0, [X0, #44]

0x421d50 CMP	W26, W19

0x421d54 B.GE	422090

0x421d58 ADD	W20, W20, #1

0x421d5c STP	X21, X22, [SP, #32]

0x421d60 ADD	W22, W0, #3

0x421d64 SUB	W25, W19, W26

0x421d68 CMP	W20, W22

0x421d6c B.GE	4220a4

0x421d70 SUB	W21, W22, W20

0x421d74 BL	403530

0x421d78 MADD	W25, W25, W21, WZR

0x421d7c ORR	W24, WZR, W0

0x421d80 BL	4033c0

0x421d84 ORR	W3, WZR, W0

0x421d88 UDIV	W2, W25, W24

0x421d8c MSUB	W1, W2, W24, W25

0x421d90 CMP	W0, W1

0x421d94 B.CC	4220bc

  (257) 0x421d98 MADD	W8, W2, W3, W1

  (257) 0x421d9c ADD	W15, W2, W8

  (257) 0x421da0 CMP	W8, W15

  (257) 0x421da4 B.CS	4220a4

(259) 0x421da8 UDIV	W5, W8, W21

(259) 0x421dac ADRP	X16,

(259) 0x421db0 STP	D8, D9, [SP, #80]

(259) 0x421db4 LDP	X14, X13, [X23]

(259) 0x421db8 ADD	X25, X16, #2088

(259) 0x421dbc CNTW	X10, ALL

(259) 0x421dc0 PTRUE	P0.B, ALL

(259) 0x421dc4 DUP	Z27.S, #2

(259) 0x421dc8 DUP	Z26.B, #255

(259) 0x421dcc FDUP	Z22.D, #240

(259) 0x421dd0 FDUP	Z21.D, #0

(259) 0x421dd4 LDP	X12, X11, [X23, #16]

(259) 0x421dd8 LDR	X17, [X23, #32]

(259) 0x421ddc STR	D10, [SP, #96]

(259) 0x421de0 MSUB	W4, W5, W21, W8

(259) 0x421de4 ADD	W24, W5, W26

(259) 0x421de8 SBFM	X18, X24, #0, #31

(259) 0x421dec ADD	W3, W4, W20

(259) 0x421df0 SUB	W26, W22, W3

(259) 0x421df4 ADD	W22, W24, #1

(259) 0x421df8 CMP	W2, W26

(259) 0x421dfc CSEL	X26, X2, X26, #9

(259) 0x421e00 ADD	W30, W8, W26

(259) 0x421e04 CMP	W8, W30

(259) 0x421e08 B.CS	422074

  (260) 0x421e0c LDR	X6, [X11]

  (260) 0x421e10 SBFM	X9, X3, #0, #31

  (260) 0x421e14 INDEX	Z16.S, W3, #1

  (260) 0x421e18 DUP	Z17.S, W24

  (260) 0x421e1c MOVZ	X0, #0

  (260) 0x421e20 DUP	Z23.S, W22

  (260) 0x421e24 LDR	X3, [X13]

  (260) 0x421e28 ORR	X8, XZR, X26

  (260) 0x421e2c WHILELO	P2.D, XZR, X26

  (260) 0x421e30 UQDECD	X8, ALL

  (260) 0x421e34 SUNPKLO	Z20.D, Z23

  (260) 0x421e38 WHILELO	P1.D, XZR, X8

  (260) 0x421e3c LDR	X7, [X11, #16]

  (260) 0x421e40 SUNPKHI	Z19.D, Z23

  (260) 0x421e44 MOVPRFX	Z25, Z17

  (260) 0x421e48 SUB	Z25.S, Z25.S, #1

  (260) 0x421e4c MADD	X23, X18, X6, X9

  (260) 0x421e50 DUP	Z7.D, X18

  (260) 0x421e54 LD1RD	{Z18.D}, P0/Z, [X12]

  (260) 0x421e58 LDR	X2, [X13, #16]

  (260) 0x421e5c LD1RD	{Z6.D}, P0/Z, [X14]

  (260) 0x421e60 LD1RD	{Z24.D}, P0/Z, [X25]

  (260) 0x421e64 MADD	X1, X18, X3, X9

  (260) 0x421e68 LDR	X4, [X17, #8]

  (260) 0x421e6c ADD	X24, X7, X23,LSL #3

  (260) 0x421e70 LDR	X6, [X12, #16]

  (260) 0x421e74 ADD	X16, X2, X1,LSL #3

  (260) 0x421e78 ADDVL	X5, X24, #1

  (260) 0x421e7c LDR	X23, [X14, #16]

  (260) 0x421e80 ADD	X9, X4, X18,LSL #3

  (260) 0x421e84 ADDVL	X7, X16, #1

    (258) 0x421e88 LD1D	{Z28.D}, P2/Z, [X16, X0,LSL #3]

    (258) 0x421e8c LD1D	{Z5.D}, P1/Z, [X7, X0,LSL #3]

    (258) 0x421e90 SUNPKLO	Z9.D, Z16

    (258) 0x421e94 SUNPKHI	Z8.D, Z16

    (258) 0x421e98 FCMGE	P4.D, P0/Z, Z28.D, #0

    (258) 0x421e9c FCMGE	P5.D, P0/Z, Z5.D, #0

    (258) 0x421ea0 SEL	Z1.D, P4, Z7.D, Z20.D

    (258) 0x421ea4 UZP1	P3.S, P4.S, P5.S

    (258) 0x421ea8 MOVPRFX	Z3, Z9

    (258) 0x421eac MLA	Z3.D, P0/M, Z6.D, Z1.D

    (258) 0x421eb0 EOR	P6.B, P0/Z, P3.B, P0.B

    (258) 0x421eb4 MAD	Z1.D, P0/M, Z18.D, Z9.D

    (258) 0x421eb8 SEL	Z0.S, P6, Z17.S, Z25.S

    (258) 0x421ebc LD1D	{Z30.D}, P2/Z, [X6, Z1.D,LSL #3]

    (258) 0x421ec0 ADD	Z0.S, P6/M, Z0.S, Z27.S

    (258) 0x421ec4 SUNPKHI	Z2.D, Z0

    (258) 0x421ec8 MAD	Z2.D, P0/M, Z6.D, Z8.D

    (258) 0x421ecc LD1D	{Z3.D}, P2/Z, [X23, Z3.D,LSL #3]

    (258) 0x421ed0 FCMLT	P7.D, P0/Z, Z28.D, #0

    (258) 0x421ed4 SUNPKLO	Z29.D, Z0

    (258) 0x421ed8 MOVPRFX	Z4, Z28

    (258) 0x421edc FABS	Z4.D, P0/M, Z28.D

    (258) 0x421ee0 LD1D	{Z0.D}, P1/Z, [X23, Z2.D,LSL #3]

    (258) 0x421ee4 FDIV	Z4.D, P0/M, Z4.D, Z30.D

    (258) 0x421ee8 MAD	Z29.D, P0/M, Z6.D, Z9.D

    (258) 0x421eec SEL	Z1.D, P7, Z7.D, Z20.D

    (258) 0x421ef0 LD1D	{Z29.D}, P2/Z, [X23, Z29.D,LSL #3]

    (258) 0x421ef4 MAD	Z1.D, P0/M, Z6.D, Z9.D

    (258) 0x421ef8 FSUB	Z10.D, Z3.D, Z29.D

    (258) 0x421efc LD1D	{Z2.D}, P2/Z, [X23, Z1.D,LSL #3]

    (258) 0x421f00 FABD	Z29.D, P0/M, Z29.D, Z3.D

    (258) 0x421f04 FSUB	Z30.D, Z2.D, Z3.D

    (258) 0x421f08 SEL	Z31.S, P3, Z17.S, Z23.S

    (258) 0x421f0c FMUL	Z10.D, Z10.D, Z30.D

    (258) 0x421f10 ADD	Z31.S, P3/M, Z31.S, Z26.S

    (258) 0x421f14 SUNPKLO	Z9.D, Z31

    (258) 0x421f18 FCMGT	P3.D, P2/Z, Z10.D, #0

    (258) 0x421f1c FABD	Z2.D, P0/M, Z2.D, Z3.D

    (258) 0x421f20 FCMGT	P4.D, P0/Z, Z30.D, #0

    (258) 0x421f24 MOVPRFX	Z1, Z4

    (258) 0x421f28 FADD	Z1.D, P0/M, Z1.D, #1

    (258) 0x421f2c LD1D	{Z30.D}, P3/Z, [X4, Z9.D,LSL #3]

    (258) 0x421f30 FCMGT	P6.D, P4/Z, Z10.D, #0

    (258) 0x421f34 MOVPRFX	Z9, Z29

    (258) 0x421f38 FMINNM	Z9.D, P0/M, Z9.D, Z2.D

    (258) 0x421f3c FMUL	Z1.D, Z1.D, Z29.D

    (258) 0x421f40 MOVPRFX	Z10, Z22

    (258) 0x421f44 FCPY	Z10.D, P6/M, #1.0000000

    (258) 0x421f48 FSUB	Z29.D, Z21.D, Z4.D

    (258) 0x421f4c FDIV	Z1.D, P0/M, Z1.D, Z30.D

    (258) 0x421f50 FMUL	Z2.D, Z29.D, Z2.D

    (258) 0x421f54 LD1RD	{Z30.D}, P0/Z, [X9]

    (258) 0x421f58 FSUBR	Z4.D, P0/M, Z4.D, #1

    (258) 0x421f5c FDIV	Z2.D, P0/M, Z2.D, Z30.D

    (258) 0x421f60 FMUL	Z29.D, Z30.D, Z24.D

    (258) 0x421f64 FMUL	Z4.D, Z4.D, Z10.D

    (258) 0x421f68 FADD	Z1.D, Z1.D, Z2.D

    (258) 0x421f6c SEL	Z10.D, P5, Z7.D, Z19.D

    (258) 0x421f70 FMUL	Z1.D, Z1.D, Z29.D

    (258) 0x421f74 FMINNM	Z1.D, P0/M, Z1.D, Z9.D

    (258) 0x421f78 MOVPRFX	Z9, Z8

    (258) 0x421f7c MLA	Z9.D, P0/M, Z6.D, Z10.D

    (258) 0x421f80 FMLA	Z3.D, P3/M, Z4.D, Z1.D

    (258) 0x421f84 LD1D	{Z2.D}, P1/Z, [X23, Z9.D,LSL #3]

    (258) 0x421f88 FMUL	Z3.D, Z28.D, Z3.D

    (258) 0x421f8c FSUB	Z1.D, Z2.D, Z0.D

    (258) 0x421f90 MAD	Z10.D, P0/M, Z18.D, Z8.D

    (258) 0x421f94 FCMLT	P8.D, P0/Z, Z5.D, #0

    (258) 0x421f98 LD1D	{Z10.D}, P1/Z, [X6, Z10.D,LSL #3]

    (258) 0x421f9c SEL	Z28.D, P8, Z7.D, Z19.D

    (258) 0x421fa0 MAD	Z28.D, P0/M, Z6.D, Z8.D

    (258) 0x421fa4 LD1D	{Z28.D}, P1/Z, [X23, Z28.D,LSL #3]

    (258) 0x421fa8 FSUB	Z8.D, Z28.D, Z2.D

    (258) 0x421fac FMUL	Z9.D, Z1.D, Z8.D

    (258) 0x421fb0 FABD	Z0.D, P0/M, Z0.D, Z2.D

    (258) 0x421fb4 FCMGT	P7.D, P1/Z, Z9.D, #0

    (258) 0x421fb8 FABD	Z28.D, P0/M, Z28.D, Z2.D

    (258) 0x421fbc MOVPRFX	Z4, Z5

    (258) 0x421fc0 FABS	Z4.D, P0/M, Z5.D

    (258) 0x421fc4 FCMGT	P5.D, P0/Z, Z8.D, #0

    (258) 0x421fc8 FDIV	Z4.D, P0/M, Z4.D, Z10.D

    (258) 0x421fcc SUNPKHI	Z31.D, Z31

    (258) 0x421fd0 MOVPRFX	Z10, Z0

    (258) 0x421fd4 FMINNM	Z10.D, P0/M, Z10.D, Z28.D

    (258) 0x421fd8 LD1D	{Z31.D}, P7/Z, [X4, Z31.D,LSL #3]

    (258) 0x421fdc MOVPRFX	Z1, Z4

    (258) 0x421fe0 FADD	Z1.D, P0/M, Z1.D, #1

    (258) 0x421fe4 FSUB	Z8.D, Z21.D, Z4.D

    (258) 0x421fe8 FCMGT	P4.D, P5/Z, Z9.D, #0

    (258) 0x421fec FMUL	Z0.D, Z1.D, Z0.D

    (258) 0x421ff0 FMUL	Z28.D, Z8.D, Z28.D

    (258) 0x421ff4 FDIV	Z0.D, P0/M, Z0.D, Z31.D

    (258) 0x421ff8 FDIV	Z28.D, P0/M, Z28.D, Z30.D

    (258) 0x421ffc FSUBR	Z4.D, P0/M, Z4.D, #1

    (258) 0x422000 FADD	Z30.D, Z0.D, Z28.D

    (258) 0x422004 MOVPRFX	Z9, Z22

    (258) 0x422008 FCPY	Z9.D, P4/M, #1.0000000

    (258) 0x42200c FMUL	Z29.D, Z30.D, Z29.D

    (258) 0x422010 FMUL	Z4.D, Z4.D, Z9.D

    (258) 0x422014 FMINNM	Z29.D, P0/M, Z29.D, Z10.D

    (258) 0x422018 FMLA	Z2.D, P7/M, Z29.D, Z4.D

    (258) 0x42201c FMUL	Z5.D, Z5.D, Z2.D

    (258) 0x422020 ST1D	{Z3.D}, P2, [X24, X0,LSL #3]

    (258) 0x422024 ST1D	{Z5.D}, P1, [X5, X0,LSL #3]

    (258) 0x422028 ADD	X0, X0, X10

    (258) 0x42202c WHILELO	P1.D, X0, X8

    (258) 0x422030 INCW	Z16.S, ALL

    (258) 0x422034 WHILELO	P2.D, X0, X26

    (258) 0x422038 B.NE	421e88

  (260) 0x42203c ADD	X18, X18, #1

  (260) 0x422040 CMP	W19, W22

  (260) 0x422044 B.LE	422084

  (260) 0x422048 SUB	W2, W15, W30

  (260) 0x42204c ORR	W26, WZR, W21

  (260) 0x422050 ORR	W8, WZR, W30

  (260) 0x422054 ORR	W24, WZR, W22

  (260) 0x422058 CMP	W2, W26

  (260) 0x42205c CSEL	X26, X2, X26, #9

  (260) 0x422060 ADD	W30, W8, W26

  (260) 0x422064 ORR	W3, WZR, W20

  (260) 0x422068 ADD	W22, W24, #1

  (260) 0x42206c CMP	W8, W30

  (260) 0x422070 B.CC	421e0c

  (261) 0x422074 ORR	W30, WZR, W8

  (261) 0x422078 ADD	X18, X18, #1

  (261) 0x42207c CMP	W19, W22

  (261) 0x422080 B.GT	422048

(259) 0x422084 LDP	D8, D9, [SP, #80]

(259) 0x422088 LDP	X21, X22, [SP, #32]

(259) 0x42208c LDR	D10, [SP, #96]

(259) 0x422090 LDP	X19, X20, [SP, #16]

(259) 0x422094 LDP	X23, X24, [SP, #48]

(259) 0x422098 LDP	X25, X26, [SP, #64]

(259) 0x42209c LDP	X29, X30, [SP], #112

(259) 0x4220a0 RET

  (257) 0x4220a4 LDP	X19, X20, [SP, #16]

  (257) 0x4220a8 LDP	X21, X22, [SP, #32]

  (257) 0x4220ac LDP	X23, X24, [SP, #48]

  (257) 0x4220b0 LDP	X25, X26, [SP, #64]

  (257) 0x4220b4 LDP	X29, X30, [SP], #112

  (257) 0x4220b8 RET

  (257) 0x4220bc ADD	W2, W2, #1

  (257) 0x4220c0 MOVZ	W1, #0

  (257) 0x4220c4 B	421d98

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:180-186,197-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.50 to 0.59 cycles (7.58x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50
cycles	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (17.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421d24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W26, [X23, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W26, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 422090 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W25, W19, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4220a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W25, W25, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W2, W25, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W1, W2, W24, W25	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 4220bc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:180-186,197-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50
cycles	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (17.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421d24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W26, [X23, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W26, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 422090 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W25, W19, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4220a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W25, W25, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W2, W25, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W1, W2, W24, W25	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 4220bc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	9.25	2.12
▼Loop 259 - advec_mom.cpp:180-211 - exec–	0	0
▼Loop 260 - advec_mom.cpp:182-211 - exec–	0	0
○Loop 258 - context.h:69-69 - exec	9.25	2.12
○Loop 257 - advec_mom.cpp:180-182 - exec	0	0
○Loop 261 - advec_mom.cpp:182-182 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code