OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage: 8.88%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

[...]

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x4219a4 STP	X29, X30, [SP, #944]!

0x4219a8 ADD	X29, SP, #0

0x4219ac STP	X19, X20, [SP, #16]

0x4219b0 STP	X25, X26, [SP, #64]

0x4219b4 LDP	W25, W20, [X0, #48]

0x4219b8 STP	X21, X22, [SP, #32]

0x4219bc LDP	W21, W2, [X0, #40]

0x4219c0 ADD	W25, W25, #1

0x4219c4 ADD	W20, W20, #3

0x4219c8 CMP	W25, W20

0x4219cc B.GE	421d04

0x4219d0 ADD	W19, W2, #3

0x4219d4 SUB	W26, W20, W25

0x4219d8 CMP	W21, W19

0x4219dc B.GE	421d04

0x4219e0 SUB	W22, W19, W21

0x4219e4 STP	X23, X24, [SP, #48]

0x4219e8 ORR	X23, XZR, X0

0x4219ec MADD	W26, W26, W22, WZR

0x4219f0 BL	403530

0x4219f4 ORR	W24, WZR, W0

0x4219f8 BL	4033c0

0x4219fc UDIV	W3, W26, W24

0x421a00 ORR	W1, WZR, W0

0x421a04 MSUB	W0, W3, W24, W26

0x421a08 CMP	W1, W0

0x421a0c B.CC	421d18

(253) 0x421a10 MADD	W8, W3, W1, W0

(253) 0x421a14 ADD	W15, W3, W8

(253) 0x421a18 CMP	W8, W15

(253) 0x421a1c B.CS	421d00

(253) 0x421a20 UDIV	W5, W8, W22

(253) 0x421a24 ADRP	X16,

(253) 0x421a28 MOVZ	W17, #0

(253) 0x421a2c ADD	X26, X16, #2088

(253) 0x421a30 CNTW	X10, ALL

(253) 0x421a34 PTRUE	P0.B, ALL

(253) 0x421a38 DUP	Z18.S, #2

(253) 0x421a3c DUP	Z17.B, #255

(253) 0x421a40 FDUP	Z16.D, #240

(253) 0x421a44 FDUP	Z7.D, #0

(253) 0x421a48 LDP	X14, X13, [X23]

(253) 0x421a4c LDP	X12, X11, [X23, #16]

(253) 0x421a50 MSUB	W4, W5, W22, W8

(253) 0x421a54 ADD	W6, W5, W25

(253) 0x421a58 LDR	X18, [X23, #32]

(253) 0x421a5c SBFM	X9, X6, #0, #31

(253) 0x421a60 ADD	W16, W4, W21

(253) 0x421a64 SUB	W19, W19, W16

(253) 0x421a68 CMP	W3, W19

(253) 0x421a6c CSEL	X2, X3, X19, #9

(253) 0x421a70 ADD	W19, W8, W2

(253) 0x421a74 CMP	W8, W19

(253) 0x421a78 B.CS	421ce8

(253) 0x421a7c HINT	#0

  (255) 0x421a80 LDR	X7, [X11]

  (255) 0x421a84 SBFM	X30, X16, #0, #31

  (255) 0x421a88 INDEX	Z5.S, W16, #1

  (255) 0x421a8c MOVZ	X0, #0

  (255) 0x421a90 ORR	X23, XZR, X2

  (255) 0x421a94 WHILELO	P2.D, XZR, X2

  (255) 0x421a98 LDR	X24, [X12]

  (255) 0x421a9c UQDECD	X23, ALL

  (255) 0x421aa0 LD1RD	{Z6.D}, P0/Z, [X26]

  (255) 0x421aa4 WHILELO	P1.D, XZR, X23

  (255) 0x421aa8 LDR	X8, [X11, #16]

  (255) 0x421aac MADD	X25, X9, X7, X30

  (255) 0x421ab0 LDR	X1, [X12, #16]

  (255) 0x421ab4 MADD	X5, X9, X24, XZR

  (255) 0x421ab8 LDR	X6, [X13]

  (255) 0x421abc ADD	X3, X8, X25,LSL #3

  (255) 0x421ac0 LDR	X24, [X14]

  (255) 0x421ac4 ADD	X16, X1, X5,LSL #3

  (255) 0x421ac8 ADDVL	X4, X3, #1

  (255) 0x421acc LDR	X5, [X18, #8]

  (255) 0x421ad0 MADD	X7, X9, X6, X30

  (255) 0x421ad4 LDR	X8, [X13, #16]

  (255) 0x421ad8 MADD	X1, X9, X24, XZR

  (255) 0x421adc LDR	X25, [X14, #16]

  (255) 0x421ae0 ADD	X30, X5, X30,LSL #3

  (255) 0x421ae4 ADD	X6, X8, X7,LSL #3

  (255) 0x421ae8 ADDVL	X24, X30, #1

  (255) 0x421aec ADD	X7, X25, X1,LSL #3

  (255) 0x421af0 ADDVL	X8, X6, #1

  (255) 0x421af4 HINT	#0

  (255) 0x421af8 HINT	#0

  (255) 0x421afc HINT	#0

    (254) 0x421b00 LD1D	{Z23.D}, P2/Z, [X6, X0,LSL #3]

    (254) 0x421b04 LD1D	{Z4.D}, P1/Z, [X8, X0,LSL #3]

    (254) 0x421b08 FCMGE	P3.D, P0/Z, Z23.D, #0

    (254) 0x421b0c FCMGE	P5.D, P0/Z, Z4.D, #0

    (254) 0x421b10 MOVPRFX	Z20, Z5

    (254) 0x421b14 SUB	Z20.S, Z20.S, #1

    (254) 0x421b18 UZP1	P6.S, P3.S, P5.S

    (254) 0x421b1c EOR	P4.B, P0/Z, P6.B, P0.B

    (254) 0x421b20 MOVPRFX	Z20.S, P4/M, Z5.S

    (254) 0x421b24 ADD	Z20.S, P4/M, Z20.S, Z18.S

    (254) 0x421b28 MOVPRFX	Z24, Z5

    (254) 0x421b2c ADD	Z24.S, Z24.S, #1

    (254) 0x421b30 SUNPKLO	Z2.D, Z5

    (254) 0x421b34 SUNPKLO	Z3.D, Z24

    (254) 0x421b38 SUNPKLO	Z19.D, Z20

    (254) 0x421b3c SEL	Z22.D, P3, Z2.D, Z3.D

    (254) 0x421b40 LD1D	{Z27.D}, P2/Z, [X7, Z19.D,LSL #3]

    (254) 0x421b44 LD1D	{Z21.D}, P2/Z, [X7, Z22.D,LSL #3]

    (254) 0x421b48 LD1D	{Z26.D}, P2/Z, [X16, Z22.D,LSL #3]

    (254) 0x421b4c FSUB	Z29.D, Z21.D, Z27.D

    (254) 0x421b50 SUNPKHI	Z0.D, Z20

    (254) 0x421b54 FCMLT	P7.D, P0/Z, Z23.D, #0

    (254) 0x421b58 SEL	Z25.D, P7, Z2.D, Z3.D

    (254) 0x421b5c LD1D	{Z30.D}, P2/Z, [X7, Z25.D,LSL #3]

    (254) 0x421b60 FSUB	Z20.D, Z30.D, Z21.D

    (254) 0x421b64 LD1D	{Z28.D}, P1/Z, [X7, Z0.D,LSL #3]

    (254) 0x421b68 FMUL	Z3.D, Z20.D, Z29.D

    (254) 0x421b6c SEL	Z19.S, P6, Z5.S, Z24.S

    (254) 0x421b70 FCMGT	P3.D, P2/Z, Z3.D, #0

    (254) 0x421b74 ADD	Z19.S, P6/M, Z19.S, Z17.S

    (254) 0x421b78 SUNPKHI	Z1.D, Z5

    (254) 0x421b7c FABD	Z27.D, P0/M, Z27.D, Z21.D

    (254) 0x421b80 FABD	Z30.D, P0/M, Z30.D, Z21.D

    (254) 0x421b84 SUNPKLO	Z0.D, Z19

    (254) 0x421b88 MOVPRFX	Z31, Z23

    (254) 0x421b8c FABS	Z31.D, P0/M, Z23.D

    (254) 0x421b90 LD1D	{Z2.D}, P3/Z, [X5, Z0.D,LSL #3]

    (254) 0x421b94 FDIV	Z31.D, P0/M, Z31.D, Z26.D

    (254) 0x421b98 FCMGT	P4.D, P0/Z, Z20.D, #0

    (254) 0x421b9c MOVPRFX	Z26, Z27

    (254) 0x421ba0 FMINNM	Z26.D, P0/M, Z26.D, Z30.D

    (254) 0x421ba4 LD1D	{Z20.D}, P2/Z, [X30, X0,LSL #3]

    (254) 0x421ba8 MOVPRFX	Z25, Z31

    (254) 0x421bac FADD	Z25.D, P0/M, Z25.D, #1

    (254) 0x421bb0 FSUB	Z29.D, Z7.D, Z31.D

    (254) 0x421bb4 FMUL	Z27.D, Z25.D, Z27.D

    (254) 0x421bb8 FMUL	Z30.D, Z29.D, Z30.D

    (254) 0x421bbc FDIV	Z27.D, P0/M, Z27.D, Z2.D

    (254) 0x421bc0 FDIV	Z30.D, P0/M, Z30.D, Z20.D

    (254) 0x421bc4 SUNPKHI	Z24.D, Z24

    (254) 0x421bc8 FADD	Z0.D, Z27.D, Z30.D

    (254) 0x421bcc SEL	Z25.D, P5, Z1.D, Z24.D

    (254) 0x421bd0 SUNPKHI	Z22.D, Z19

    (254) 0x421bd4 LD1D	{Z30.D}, P1/Z, [X7, Z25.D,LSL #3]

    (254) 0x421bd8 FMUL	Z19.D, Z20.D, Z6.D

    (254) 0x421bdc FCMLT	P8.D, P0/Z, Z4.D, #0

    (254) 0x421be0 LD1D	{Z20.D}, P1/Z, [X16, Z25.D,LSL #3]

    (254) 0x421be4 FMUL	Z27.D, Z0.D, Z19.D

    (254) 0x421be8 FCMGT	P6.D, P4/Z, Z3.D, #0

    (254) 0x421bec FMINNM	Z27.D, P0/M, Z27.D, Z26.D

    (254) 0x421bf0 MOVPRFX	Z3, Z16

    (254) 0x421bf4 FCPY	Z3.D, P6/M, #1.0000000

    (254) 0x421bf8 FSUBR	Z31.D, P0/M, Z31.D, #1

    (254) 0x421bfc FMUL	Z31.D, Z31.D, Z3.D

    (254) 0x421c00 MOVPRFX	Z2, Z21

    (254) 0x421c04 FMLA	Z2.D, P3/M, Z31.D, Z27.D

    (254) 0x421c08 SEL	Z21.D, P8, Z1.D, Z24.D

    (254) 0x421c0c FMUL	Z29.D, Z23.D, Z2.D

    (254) 0x421c10 LD1D	{Z1.D}, P1/Z, [X7, Z21.D,LSL #3]

    (254) 0x421c14 FSUB	Z23.D, Z30.D, Z28.D

    (254) 0x421c18 FSUB	Z26.D, Z1.D, Z30.D

    (254) 0x421c1c FABD	Z1.D, P0/M, Z1.D, Z30.D

    (254) 0x421c20 LD1D	{Z24.D}, P1/Z, [X24, X0,LSL #3]

    (254) 0x421c24 FMUL	Z3.D, Z23.D, Z26.D

    (254) 0x421c28 FABD	Z28.D, P0/M, Z28.D, Z30.D

    (254) 0x421c2c FCMGT	P5.D, P1/Z, Z3.D, #0

    (254) 0x421c30 MOVPRFX	Z31, Z28

    (254) 0x421c34 FMINNM	Z31.D, P0/M, Z31.D, Z1.D

    (254) 0x421c38 LD1D	{Z22.D}, P5/Z, [X5, Z22.D,LSL #3]

    (254) 0x421c3c MOVPRFX	Z19, Z4

    (254) 0x421c40 FABS	Z19.D, P0/M, Z4.D

    (254) 0x421c44 FCMGT	P7.D, P0/Z, Z26.D, #0

    (254) 0x421c48 FDIV	Z19.D, P0/M, Z19.D, Z20.D

    (254) 0x421c4c FMUL	Z21.D, Z24.D, Z6.D

    (254) 0x421c50 MOVPRFX	Z0, Z19

    (254) 0x421c54 FADD	Z0.D, P0/M, Z0.D, #1

    (254) 0x421c58 FSUB	Z27.D, Z7.D, Z19.D

    (254) 0x421c5c FMUL	Z28.D, Z0.D, Z28.D

    (254) 0x421c60 FMUL	Z25.D, Z27.D, Z1.D

    (254) 0x421c64 FDIV	Z28.D, P0/M, Z28.D, Z22.D

    (254) 0x421c68 FDIV	Z25.D, P0/M, Z25.D, Z24.D

    (254) 0x421c6c FSUBR	Z19.D, P0/M, Z19.D, #1

    (254) 0x421c70 FADD	Z2.D, Z28.D, Z25.D

    (254) 0x421c74 FCMGT	P3.D, P7/Z, Z3.D, #0

    (254) 0x421c78 FMUL	Z20.D, Z2.D, Z21.D

    (254) 0x421c7c MOVPRFX	Z1, Z16

    (254) 0x421c80 FCPY	Z1.D, P3/M, #1.0000000

    (254) 0x421c84 FMINNM	Z20.D, P0/M, Z20.D, Z31.D

    (254) 0x421c88 FMUL	Z23.D, Z19.D, Z1.D

    (254) 0x421c8c MOVPRFX	Z26, Z30

    (254) 0x421c90 FMLA	Z26.D, P5/M, Z23.D, Z20.D

    (254) 0x421c94 FMUL	Z4.D, Z4.D, Z26.D

    (254) 0x421c98 ST1D	{Z29.D}, P2, [X3, X0,LSL #3]

    (254) 0x421c9c ST1D	{Z4.D}, P1, [X4, X0,LSL #3]

    (254) 0x421ca0 ADD	X0, X0, X10

    (254) 0x421ca4 WHILELO	P1.D, X0, X23

    (254) 0x421ca8 INCW	Z5.S, ALL

    (254) 0x421cac WHILELO	P2.D, X0, X2

    (254) 0x421cb0 B.NE	421b00

  (255) 0x421cb4 ADD	X9, X9, #1

  (255) 0x421cb8 ADD	W2, W17, W9

  (255) 0x421cbc CMP	W20, W2

  (255) 0x421cc0 B.LE	421d00

  (255) 0x421cc4 SUB	W3, W15, W19

  (255) 0x421cc8 ORR	W8, WZR, W19

  (255) 0x421ccc ORR	W19, WZR, W22

  (255) 0x421cd0 ORR	W16, WZR, W21

  (255) 0x421cd4 CMP	W3, W19

  (255) 0x421cd8 CSEL	X2, X3, X19, #9

  (255) 0x421cdc ADD	W19, W8, W2

  (255) 0x421ce0 CMP	W8, W19

  (255) 0x421ce4 B.CC	421a80

  (256) 0x421ce8 ADD	X9, X9, #1

  (256) 0x421cec ORR	W19, WZR, W8

  (256) 0x421cf0 ADD	W2, W17, W9

  (256) 0x421cf4 CMP	W20, W2

  (256) 0x421cf8 B.GT	421cc4

(253) 0x421cfc HINT	#0

(253) 0x421d00 LDP	X23, X24, [SP, #48]

(253) 0x421d04 LDP	X19, X20, [SP, #16]

(253) 0x421d08 LDP	X21, X22, [SP, #32]

(253) 0x421d0c LDP	X25, X26, [SP, #64]

(253) 0x421d10 LDP	X29, X30, [SP], #80

(253) 0x421d14 RET

(253) 0x421d18 ADD	W3, W3, #1

(253) 0x421d1c MOVZ	W0, #0

(253) 0x421d20 B	421a10

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:108-114,120-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.50 to 0.62 cycles (7.20x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.38
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (17.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4219a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W21, W2, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W20, W20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421d04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W20, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421d04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W22, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W22, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 421d18 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:108-114,120-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.38
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (17.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4219a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W21, W2, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W20, W20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421d04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W20, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421d04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W22, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W22, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 421d18 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	8.88	2.04
▼Loop 253 - advec_mom.cpp:108-139 - exec–	0	0
○Loop 256 - advec_mom.cpp:110-139 - exec	0	0
▼Loop 255 - advec_mom.cpp:110-139 - exec–	0	0
○Loop 254 - context.h:69-69 - exec	8.88	2.04

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code