OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage: 1.61%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

0x4213c4 STP	X29, X30, [SP, #912]!

0x4213c8 ADD	X29, SP, #0

0x4213cc STP	X19, X20, [SP, #16]

0x4213d0 LDR	W20, [X0, #52]

0x4213d4 STP	X21, X22, [SP, #32]

0x4213d8 ORR	X22, XZR, X0

0x4213dc LDR	W3, [X22, #48]

0x4213e0 ADD	W20, W20, #4

0x4213e4 LDR	W21, [X0, #40]

0x4213e8 LDR	W0, [X0, #44]

0x4213ec CMP	W3, W20

0x4213f0 B.GE	4215fc

0x4213f4 ADD	W21, W21, #1

0x4213f8 ADD	W19, W0, #3

0x4213fc STP	X25, X26, [SP, #64]

0x421400 SUB	W25, W20, W3

0x421404 STR	W3, [SP, #108]

0x421408 CMP	W21, W19

0x42140c B.GE	421618

0x421410 STP	X23, X24, [SP, #48]

0x421414 SUB	W24, W19, W21

0x421418 MADD	W26, W25, W24, WZR

0x42141c STP	X27, X28, [SP, #80]

0x421420 BL	403530

0x421424 ORR	W23, WZR, W0

0x421428 BL	4033c0

0x42142c UDIV	W1, W26, W23

0x421430 LDR	W4, [SP, #108]

0x421434 ORR	W2, WZR, W0

0x421438 MSUB	W5, W1, W23, W26

0x42143c CMP	W0, W5

0x421440 B.CC	42160c

(241) 0x421444 MADD	W11, W1, W2, W5

(241) 0x421448 ADD	W28, W1, W11

(241) 0x42144c CMP	W11, W28

(241) 0x421450 B.CS	4215f0

(241) 0x421454 UDIV	W16, W11, W24

(241) 0x421458 CNTD	X15, ALL

(241) 0x42145c PTRUE	P1.B, ALL

(241) 0x421460 FDUP	Z5.D, #80

(241) 0x421464 LDP	X27, X26, [X22]

(241) 0x421468 LDP	X25, X23, [X22, #16]

(241) 0x42146c LDR	X22, [X22, #32]

(241) 0x421470 MSUB	W9, W16, W24, W11

(241) 0x421474 ADD	W16, W16, W4

(241) 0x421478 SBFM	X14, X16, #0, #31

(241) 0x42147c ADD	W7, W9, W21

(241) 0x421480 SUB	W30, W19, W7

(241) 0x421484 CMP	W1, W30

(241) 0x421488 CSEL	X1, X1, X30, #9

(241) 0x42148c ADD	W30, W11, W1

(241) 0x421490 CMP	W11, W30

(241) 0x421494 B.CS	4215dc

(241) 0x421498 HINT	#0

(241) 0x42149c HINT	#0

  (243) 0x4214a0 LDR	X8, [X22]

  (243) 0x4214a4 SUB	W6, W16, #1

  (243) 0x4214a8 SBFM	X12, X7, #0, #31

  (243) 0x4214ac SBFM	X13, X6, #0, #31

  (243) 0x4214b0 MOVZ	X0, #0

  (243) 0x4214b4 WHILELO	P0.D, XZR, X1

  (243) 0x4214b8 LDR	X18, [X22, #16]

  (243) 0x4214bc LDR	X6, [X27]

  (243) 0x4214c0 MADD	X7, X13, X8, X12

  (243) 0x4214c4 MADD	X10, X14, X8, X12

  (243) 0x4214c8 LDR	X2, [X23]

  (243) 0x4214cc UBFM	X17, X7, #61, #60

  (243) 0x4214d0 LDR	X4, [X25]

  (243) 0x4214d4 UBFM	X3, X10, #61, #60

  (243) 0x4214d8 SUB	X11, X17, #8

  (243) 0x4214dc MADD	X8, X13, X6, X12

  (243) 0x4214e0 SUB	X19, X3, #8

  (243) 0x4214e4 ADD	X7, X18, X17

  (243) 0x4214e8 LDR	X17, [X26]

  (243) 0x4214ec ADD	X10, X18, X19

  (243) 0x4214f0 ADD	X5, X18, X3

  (243) 0x4214f4 MADD	X19, X14, X6, X12

  (243) 0x4214f8 LDR	X3, [X27, #16]

  (243) 0x4214fc MADD	X9, X14, X2, X12

  (243) 0x421500 UBFM	X2, X8, #61, #60

  (243) 0x421504 ADD	X11, X18, X11

  (243) 0x421508 MADD	X18, X14, X4, X12

  (243) 0x42150c UBFM	X6, X19, #61, #60

  (243) 0x421510 MADD	X4, X13, X17, X12

  (243) 0x421514 SUB	X13, X2, #8

  (243) 0x421518 MADD	X17, X17, X14, X12

  (243) 0x42151c SUB	X12, X6, #8

  (243) 0x421520 ADD	X8, X3, X2

  (243) 0x421524 ADD	X13, X3, X13

  (243) 0x421528 ADD	X12, X3, X12

  (243) 0x42152c ADD	X6, X3, X6

  (243) 0x421530 LDR	X3, [X23, #16]

  (243) 0x421534 ADD	X19, X3, X9,LSL #3

  (243) 0x421538 LDR	X9, [X26, #16]

  (243) 0x42153c ADD	X2, X9, X4,LSL #3

  (243) 0x421540 ADD	X4, X9, X17,LSL #3

  (243) 0x421544 LDR	X17, [X25, #16]

  (243) 0x421548 ADD	X18, X17, X18,LSL #3

    (242) 0x42154c LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

    (242) 0x421550 LD1D	{Z1.D}, P0/Z, [X5, X0,LSL #3]

    (242) 0x421554 LD1D	{Z2.D}, P0/Z, [X8, X0,LSL #3]

    (242) 0x421558 LD1D	{Z6.D}, P0/Z, [X7, X0,LSL #3]

    (242) 0x42155c LD1D	{Z4.D}, P0/Z, [X12, X0,LSL #3]

    (242) 0x421560 LD1D	{Z7.D}, P0/Z, [X10, X0,LSL #3]

    (242) 0x421564 LD1D	{Z16.D}, P0/Z, [X13, X0,LSL #3]

    (242) 0x421568 LD1D	{Z18.D}, P0/Z, [X11, X0,LSL #3]

    (242) 0x42156c FMUL	Z3.D, Z1.D, Z0.D

    (242) 0x421570 FMUL	Z17.D, Z7.D, Z4.D

    (242) 0x421574 FMAD	Z6.D, P1/M, Z2.D, Z3.D

    (242) 0x421578 FMAD	Z18.D, P1/M, Z16.D, Z17.D

    (242) 0x42157c FADD	Z19.D, Z6.D, Z18.D

    (242) 0x421580 FMUL	Z20.D, Z19.D, Z5.D

    (242) 0x421584 ST1D	{Z20.D}, P0, [X18, X0,LSL #3]

    (242) 0x421588 LD1D	{Z21.D}, P0/Z, [X2, X0,LSL #3]

    (242) 0x42158c LD1D	{Z22.D}, P0/Z, [X4, X0,LSL #3]

    (242) 0x421590 FSUB	Z23.D, Z22.D, Z21.D

    (242) 0x421594 FADD	Z24.D, Z23.D, Z20.D

    (242) 0x421598 ST1D	{Z24.D}, P0, [X19, X0,LSL #3]

    (242) 0x42159c ADD	X0, X0, X15

    (242) 0x4215a0 WHILELO	P0.D, X0, X1

    (242) 0x4215a4 B.NE	42154c

  (243) 0x4215a8 ADD	W16, W16, #1

  (243) 0x4215ac ADD	X14, X14, #1

  (243) 0x4215b0 CMP	W20, W16

  (243) 0x4215b4 B.LE	4215f0

  (243) 0x4215b8 SUB	W1, W28, W30

  (243) 0x4215bc ORR	W11, WZR, W30

  (243) 0x4215c0 ORR	W30, WZR, W24

  (243) 0x4215c4 ORR	W7, WZR, W21

  (243) 0x4215c8 CMP	W1, W30

  (243) 0x4215cc CSEL	X1, X1, X30, #9

  (243) 0x4215d0 ADD	W30, W11, W1

  (243) 0x4215d4 CMP	W11, W30

  (243) 0x4215d8 B.CC	4214a0

  (244) 0x4215dc ADD	W16, W16, #1

  (244) 0x4215e0 ORR	W30, WZR, W11

  (244) 0x4215e4 ADD	X14, X14, #1

  (244) 0x4215e8 CMP	W20, W16

  (244) 0x4215ec B.GT	4215b8

(241) 0x4215f0 LDP	X23, X24, [SP, #48]

(241) 0x4215f4 LDP	X25, X26, [SP, #64]

(241) 0x4215f8 LDP	X27, X28, [SP, #80]

(241) 0x4215fc LDP	X19, X20, [SP, #16]

(241) 0x421600 LDP	X21, X22, [SP, #32]

(241) 0x421604 LDP	X29, X30, [SP], #112

(241) 0x421608 RET

(241) 0x42160c ADD	W1, W1, #1

(241) 0x421610 MOVZ	W5, #0

(241) 0x421614 B	421444

0x421618 LDP	X25, X26, [SP, #64]

0x42161c B	4215fc

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.50 to 0.59 cycles (7.58x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	4.50	4.17	4.33	3.50	3.50
cycles	3.00	3.00	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	4.50	4.17	4.33	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	4.25
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
46% of peak store performance is reached (22.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4213c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W20, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [X22, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4215fc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W25, W20, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W3, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421618 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W24, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W25, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W23	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
LDR W4, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W5, W1, W23, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42160c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4215fc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	4.50	4.17	4.33	3.50	3.50
cycles	3.00	3.00	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	4.50	4.17	4.33	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	4.25
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
46% of peak store performance is reached (22.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4213c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W20, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [X22, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4215fc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W25, W20, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W3, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421618 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W24, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W25, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W23	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
LDR W4, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W5, W1, W23, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42160c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4215fc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.61	0.37
▼Loop 241 - advec_mom.cpp:167-172 - exec–	0	0
○Loop 244 - advec_mom.cpp:169-169 - exec	0	0
▼Loop 243 - advec_mom.cpp:169-172 - exec–	0	0
○Loop 242 - advec_mom.cpp:170-172 - exec	1.61	0.37

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code