OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage: 2.5%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

0x421204 STP	X29, X30, [SP, #944]!

0x421208 ADD	X29, SP, #0

0x42120c STP	X19, X20, [SP, #16]

0x421210 STP	X25, X26, [SP, #64]

0x421214 LDP	W25, W19, [X0, #40]

0x421218 STP	X23, X24, [SP, #48]

0x42121c ORR	X23, XZR, X0

0x421220 LDR	W20, [X0, #32]

0x421224 ADD	W25, W25, #1

0x421228 ADD	W19, W19, #3

0x42122c LDR	W0, [X0, #36]

0x421230 CMP	W25, W19

0x421234 B.GE	4213a4

0x421238 ADD	W20, W20, #1

0x42123c STP	X21, X22, [SP, #32]

0x421240 ADD	W22, W0, #3

0x421244 SUB	W26, W19, W25

0x421248 CMP	W20, W22

0x42124c B.GE	4213a0

0x421250 SUB	W21, W22, W20

0x421254 BL	403530

0x421258 MADD	W26, W26, W21, WZR

0x42125c ORR	W24, WZR, W0

0x421260 BL	4033c0

0x421264 ORR	W1, WZR, W0

0x421268 UDIV	W2, W26, W24

0x42126c MSUB	W3, W2, W24, W26

0x421270 CMP	W0, W3

0x421274 B.CC	4213b8

(237) 0x421278 MADD	W18, W2, W1, W3

(237) 0x42127c ADD	W14, W2, W18

(237) 0x421280 CMP	W18, W14

(237) 0x421284 B.CS	4213a0

(237) 0x421288 UDIV	W4, W18, W21

(237) 0x42128c MOVZ	W15, #0

(237) 0x421290 CNTD	X8, ALL

(237) 0x421294 PTRUE	P1.B, ALL

(237) 0x421298 LDP	X13, X12, [X23]

(237) 0x42129c LDP	X11, X10, [X23, #16]

(237) 0x4212a0 MSUB	W5, W4, W21, W18

(237) 0x4212a4 ADD	W6, W4, W25

(237) 0x4212a8 SBFM	X7, X6, #0, #31

(237) 0x4212ac ADD	W24, W5, W20

(237) 0x4212b0 SUB	W9, W22, W24

(237) 0x4212b4 CMP	W2, W9

(237) 0x4212b8 CSEL	X30, X2, X9, #9

(237) 0x4212bc ADD	W9, W18, W30

(237) 0x4212c0 CMP	W18, W9

(237) 0x4212c4 B.CS	421384

  (239) 0x4212c8 LDR	X16, [X10]

  (239) 0x4212cc SBFM	X23, X24, #0, #31

  (239) 0x4212d0 MOVZ	X0, #0

  (239) 0x4212d4 WHILELO	P0.D, XZR, X30

  (239) 0x4212d8 LDR	X22, [X11]

  (239) 0x4212dc LDR	X1, [X12]

  (239) 0x4212e0 MADD	X17, X7, X16, X23

  (239) 0x4212e4 LDR	X5, [X13]

  (239) 0x4212e8 MADD	X24, X7, X22, X23

  (239) 0x4212ec LDR	X18, [X11, #16]

  (239) 0x4212f0 UBFM	X25, X17, #61, #60

  (239) 0x4212f4 MADD	X3, X7, X1, X23

  (239) 0x4212f8 SUB	X26, X25, #8

  (239) 0x4212fc LDR	X4, [X12, #16]

  (239) 0x421300 MADD	X23, X7, X5, X23

  (239) 0x421304 LDR	X6, [X13, #16]

  (239) 0x421308 ADD	X2, X18, X24,LSL #3

  (239) 0x42130c LDR	X22, [X10, #16]

  (239) 0x421310 ADD	X16, X4, X3,LSL #3

  (239) 0x421314 ADD	X17, X6, X23,LSL #3

  (239) 0x421318 ADD	X26, X22, X26

  (239) 0x42131c ADD	X25, X22, X25

    (238) 0x421320 LD1D	{Z2.D}, P0/Z, [X17, X0,LSL #3]

    (238) 0x421324 LD1D	{Z1.D}, P0/Z, [X2, X0,LSL #3]

    (238) 0x421328 LD1D	{Z3.D}, P0/Z, [X25, X0,LSL #3]

    (238) 0x42132c LD1D	{Z0.D}, P0/Z, [X26, X0,LSL #3]

    (238) 0x421330 LD1D	{Z4.D}, P0/Z, [X16, X0,LSL #3]

    (238) 0x421334 FNMSB	Z1.D, P1/M, Z2.D, Z3.D

    (238) 0x421338 FADD	Z5.D, Z0.D, Z1.D

    (238) 0x42133c FDIV	Z5.D, P1/M, Z5.D, Z4.D

    (238) 0x421340 ST1D	{Z5.D}, P0, [X17, X0,LSL #3]

    (238) 0x421344 ADD	X0, X0, X8

    (238) 0x421348 WHILELO	P0.D, X0, X30

    (238) 0x42134c B.NE	421320

  (239) 0x421350 ADD	X7, X7, #1

  (239) 0x421354 ADD	W30, W15, W7

  (239) 0x421358 CMP	W19, W30

  (239) 0x42135c B.LE	4213a0

  (239) 0x421360 SUB	W2, W14, W9

  (239) 0x421364 ORR	W18, WZR, W9

  (239) 0x421368 ORR	W9, WZR, W21

  (239) 0x42136c ORR	W24, WZR, W20

  (239) 0x421370 CMP	W2, W9

  (239) 0x421374 CSEL	X30, X2, X9, #9

  (239) 0x421378 ADD	W9, W18, W30

  (239) 0x42137c CMP	W18, W9

  (239) 0x421380 B.CC	4212c8

  (240) 0x421384 ADD	X7, X7, #1

  (240) 0x421388 ORR	W9, WZR, W18

  (240) 0x42138c ADD	W30, W15, W7

  (240) 0x421390 CMP	W19, W30

  (240) 0x421394 B.GT	421360

(237) 0x421398 HINT	#0

(237) 0x42139c HINT	#0

(237) 0x4213a0 LDP	X21, X22, [SP, #32]

(237) 0x4213a4 LDP	X19, X20, [SP, #16]

(237) 0x4213a8 LDP	X23, X24, [SP, #48]

(237) 0x4213ac LDP	X25, X26, [SP, #64]

(237) 0x4213b0 LDP	X29, X30, [SP], #80

(237) 0x4213b4 RET

(237) 0x4213b8 ADD	W2, W2, #1

(237) 0x4213bc MOVZ	W3, #0

(237) 0x4213c0 B	421278

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:146-149

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421204

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4213a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4213a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W2, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W2, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 4213b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:146-149

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421204

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4213a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4213a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W2, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W2, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 4213b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.5	0.57
▼Loop 237 - advec_mom.cpp:146-149 - exec–	0	0
○Loop 240 - advec_mom.cpp:148-149 - exec	0	0
▼Loop 239 - advec_mom.cpp:148-149 - exec–	0	0
○Loop 238 - advec_mom.cpp:149-149 - exec	2.5	0.57

Report Configuration

Vectorization

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Matching between your function (in the source code) and the binary function

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code