OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:85-88 [...]	Coverage: 0.52%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 85 - 88

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

0x421044 STP	X29, X30, [SP, #944]!

0x421048 ADD	X29, SP, #0

0x42104c STP	X19, X20, [SP, #16]

0x421050 LDP	W7, W19, [X0, #24]

0x421054 STP	X21, X22, [SP, #32]

0x421058 STP	X23, X24, [SP, #48]

0x42105c ADD	W22, W7, #1

0x421060 ADD	W19, W19, #3

0x421064 LDP	W20, W23, [X0, #16]

0x421068 CMP	W22, W19

0x42106c B.GE	4211e4

0x421070 SUB	W20, W20, #1

0x421074 ADD	W23, W23, #4

0x421078 STP	X25, X26, [SP, #64]

0x42107c SUB	W26, W19, W22

0x421080 CMP	W20, W23

0x421084 B.GE	4211e0

0x421088 SUB	W21, W23, W20

0x42108c ORR	X25, XZR, X0

0x421090 BL	403530

0x421094 MADD	W26, W26, W21, WZR

0x421098 ORR	W24, WZR, W0

0x42109c BL	4033c0

0x4210a0 ORR	W2, WZR, W0

0x4210a4 UDIV	W1, W26, W24

0x4210a8 MSUB	W3, W1, W24, W26

0x4210ac CMP	W0, W3

0x4210b0 B.CC	4211f8

(233) 0x4210b4 MADD	W15, W1, W2, W3

(233) 0x4210b8 ADD	W13, W1, W15

(233) 0x4210bc CMP	W15, W13

(233) 0x4210c0 B.CS	4211e0

(233) 0x4210c4 UDIV	W0, W15, W21

(233) 0x4210c8 CNTD	X8, ALL

(233) 0x4210cc FDUP	Z3.D, #80

(233) 0x4210d0 LDP	X12, X11, [X25]

(233) 0x4210d4 MSUB	W14, W0, W21, W15

(233) 0x4210d8 ADD	W7, W0, W22

(233) 0x4210dc SBFM	X9, X7, #0, #31

(233) 0x4210e0 ADD	W16, W14, W20

(233) 0x4210e4 SUB	W17, W23, W16

(233) 0x4210e8 CMP	W1, W17

(233) 0x4210ec CSEL	X17, X1, X17, #9

(233) 0x4210f0 ADD	W10, W15, W17

(233) 0x4210f4 CMP	W15, W10

(233) 0x4210f8 B.CS	4211c4

(233) 0x4210fc HINT	#0

  (235) 0x421100 LDR	X23, [X12]

  (235) 0x421104 SUB	W4, W7, #1

  (235) 0x421108 SBFM	X18, X16, #0, #31

  (235) 0x42110c SBFM	X6, X4, #0, #31

  (235) 0x421110 ADD	X5, X18, #1

  (235) 0x421114 WHILELO	P0.D, XZR, X17

  (235) 0x421118 LDR	X15, [X11]

  (235) 0x42111c MOVZ	X0, #0

  (235) 0x421120 LDR	X25, [X12, #16]

  (235) 0x421124 MADD	X26, X6, X23, XZR

  (235) 0x421128 LDR	X16, [X11, #16]

  (235) 0x42112c MADD	X24, X9, X23, XZR

  (235) 0x421130 MADD	X30, X9, X15, X18

  (235) 0x421134 ADD	X2, X26, X5

  (235) 0x421138 ADD	X1, X26, X18

  (235) 0x42113c ADD	X14, X24, X18

  (235) 0x421140 ADD	X3, X24, X5

  (235) 0x421144 ADD	X18, X25, X1,LSL #3

  (235) 0x421148 ADD	X6, X25, X2,LSL #3

  (235) 0x42114c ADD	X22, X16, X30,LSL #3

  (235) 0x421150 ADD	X5, X25, X3,LSL #3

  (235) 0x421154 ADD	X4, X25, X14,LSL #3

  (235) 0x421158 HINT	#0

  (235) 0x42115c HINT	#0

    (234) 0x421160 LD1D	{Z0.D}, P0/Z, [X18, X0,LSL #3]

    (234) 0x421164 LD1D	{Z1.D}, P0/Z, [X4, X0,LSL #3]

    (234) 0x421168 LD1D	{Z2.D}, P0/Z, [X6, X0,LSL #3]

    (234) 0x42116c LD1D	{Z5.D}, P0/Z, [X5, X0,LSL #3]

    (234) 0x421170 FADD	Z4.D, Z1.D, Z0.D

    (234) 0x421174 FADD	Z6.D, Z5.D, Z2.D

    (234) 0x421178 FADD	Z7.D, Z6.D, Z4.D

    (234) 0x42117c FMUL	Z16.D, Z7.D, Z3.D

    (234) 0x421180 ST1D	{Z16.D}, P0, [X22, X0,LSL #3]

    (234) 0x421184 ADD	X0, X0, X8

    (234) 0x421188 WHILELO	P0.D, X0, X17

    (234) 0x42118c B.NE	421160

  (235) 0x421190 ADD	W7, W7, #1

  (235) 0x421194 ADD	X9, X9, #1

  (235) 0x421198 CMP	W19, W7

  (235) 0x42119c B.LE	4211e0

  (235) 0x4211a0 SUB	W1, W13, W10

  (235) 0x4211a4 ORR	W17, WZR, W21

  (235) 0x4211a8 ORR	W15, WZR, W10

  (235) 0x4211ac CMP	W1, W17

  (235) 0x4211b0 CSEL	X17, X1, X17, #9

  (235) 0x4211b4 ADD	W10, W15, W17

  (235) 0x4211b8 ORR	W16, WZR, W20

  (235) 0x4211bc CMP	W15, W10

  (235) 0x4211c0 B.CC	421100

  (236) 0x4211c4 ADD	W7, W7, #1

  (236) 0x4211c8 ORR	W10, WZR, W15

  (236) 0x4211cc ADD	X9, X9, #1

  (236) 0x4211d0 CMP	W19, W7

  (236) 0x4211d4 B.GT	4211a0

(233) 0x4211d8 HINT	#0

(233) 0x4211dc HINT	#0

(233) 0x4211e0 LDP	X25, X26, [SP, #64]

(233) 0x4211e4 LDP	X19, X20, [SP, #16]

(233) 0x4211e8 LDP	X21, X22, [SP, #32]

(233) 0x4211ec LDP	X23, X24, [SP, #48]

(233) 0x4211f0 LDP	X29, X30, [SP], #80

(233) 0x4211f4 RET

(233) 0x4211f8 ADD	W1, W1, #1

(233) 0x4211fc MOVZ	W3, #0

(233) 0x421200 B	4210b4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:85-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.50
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421044

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W7, W19, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP W20, W23, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W22, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4211e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W23, W23, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W26, W19, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4211e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W23, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 4211f8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:85-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.50
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421044

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W7, W19, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP W20, W23, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W22, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4211e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W23, W23, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W26, W19, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4211e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W23, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 4211f8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	0.52	0.12
▼Loop 233 - advec_mom.cpp:85-88 - exec–	0	0
○Loop 236 - advec_mom.cpp:87-87 - exec	0	0
▼Loop 235 - advec_mom.cpp:87-88 - exec–	0	0
○Loop 234 - advec_mom.cpp:88-88 - exec	0.52	0.12

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Vectorization

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code