OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage: 1.41%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

0x420de0 STP	X29, X30, [SP, #912]!

0x420de4 ADD	X29, SP, #0

0x420de8 STP	X19, X20, [SP, #16]

0x420dec ORR	X20, XZR, X0

0x420df0 LDP	W3, W19, [X0, #48]

0x420df4 STP	X21, X22, [SP, #32]

0x420df8 LDR	W0, [X0, #44]

0x420dfc ADD	W1, W3, #1

0x420e00 ADD	W19, W19, #3

0x420e04 LDR	W22, [X20, #40]

0x420e08 CMP	W1, W19

0x420e0c B.GE	421010

0x420e10 STP	X23, X24, [SP, #48]

0x420e14 SUB	W24, W19, W1

0x420e18 STP	X27, X28, [SP, #80]

0x420e1c ADD	W28, W0, #4

0x420e20 STR	W1, [SP, #108]

0x420e24 CMP	W22, W28

0x420e28 B.GE	421020

0x420e2c SUB	W23, W28, W22

0x420e30 BL	403530

0x420e34 MADD	W27, W24, W23, WZR

0x420e38 ORR	W21, WZR, W0

0x420e3c BL	4033c0

0x420e40 LDR	W5, [SP, #108]

0x420e44 ORR	W2, WZR, W0

0x420e48 UDIV	W6, W27, W21

0x420e4c MSUB	W4, W6, W21, W27

0x420e50 CMP	W0, W4

0x420e54 B.CC	421038

  (228) 0x420e58 MADD	W12, W6, W2, W4

  (228) 0x420e5c ADD	W27, W6, W12

  (228) 0x420e60 CMP	W12, W27

  (228) 0x420e64 B.CS	421020

(230) 0x420e68 UDIV	W16, W12, W23

(230) 0x420e6c STP	X25, X26, [SP, #64]

(230) 0x420e70 CNTD	X15, ALL

(230) 0x420e74 PTRUE	P1.B, ALL

(230) 0x420e78 FDUP	Z5.D, #80

(230) 0x420e7c LDP	X26, X25, [X20]

(230) 0x420e80 LDP	X24, X21, [X20, #16]

(230) 0x420e84 MSUB	W7, W16, W23, W12

(230) 0x420e88 ADD	W16, W16, W5

(230) 0x420e8c LDR	X20, [X20, #32]

(230) 0x420e90 SBFM	X13, X16, #0, #31

(230) 0x420e94 ADD	W7, W7, W22

(230) 0x420e98 SUB	W1, W28, W7

(230) 0x420e9c CMP	W6, W1

(230) 0x420ea0 CSEL	X1, X6, X1, #9

(230) 0x420ea4 ADD	W18, W12, W1

(230) 0x420ea8 CMP	W12, W18

(230) 0x420eac B.CS	420ff0

  (231) 0x420eb0 LDR	X11, [X20]

  (231) 0x420eb4 SUB	W8, W16, #1

  (231) 0x420eb8 SBFM	X9, X7, #0, #31

  (231) 0x420ebc SBFM	X10, X8, #0, #31

  (231) 0x420ec0 MOVZ	X0, #0

  (231) 0x420ec4 WHILELO	P0.D, XZR, X1

  (231) 0x420ec8 LDR	X5, [X26]

  (231) 0x420ecc LDR	X12, [X21]

  (231) 0x420ed0 LDR	X14, [X24]

  (231) 0x420ed4 MADD	X4, X10, X5, X9

  (231) 0x420ed8 LDR	X30, [X25]

  (231) 0x420edc MADD	X10, X10, X11, X9

  (231) 0x420ee0 MADD	X3, X13, X12, X9

  (231) 0x420ee4 MADD	X12, X13, X5, X9

  (231) 0x420ee8 LDR	X17, [X20, #16]

  (231) 0x420eec UBFM	X7, X4, #61, #60

  (231) 0x420ef0 MADD	X28, X13, X14, X9

  (231) 0x420ef4 SUB	X4, X7, #8

  (231) 0x420ef8 LDR	X6, [X26, #16]

  (231) 0x420efc MADD	X2, X13, X30, X9

  (231) 0x420f00 UBFM	X30, X12, #61, #60

  (231) 0x420f04 MADD	X9, X13, X11, X9

  (231) 0x420f08 SUB	X11, X30, #8

  (231) 0x420f0c UBFM	X14, X2, #61, #60

  (231) 0x420f10 UBFM	X2, X10, #61, #60

  (231) 0x420f14 UBFM	X5, X9, #61, #60

  (231) 0x420f18 SUB	X10, X2, #8

  (231) 0x420f1c SUB	X9, X5, #8

  (231) 0x420f20 ADD	X12, X6, X4

  (231) 0x420f24 LDR	X4, [X25, #16]

  (231) 0x420f28 ADD	X7, X6, X7

  (231) 0x420f2c ADD	X11, X6, X11

  (231) 0x420f30 ADD	X10, X17, X10

  (231) 0x420f34 ADD	X6, X6, X30

  (231) 0x420f38 LDR	X30, [X24, #16]

  (231) 0x420f3c ADD	X2, X17, X2

  (231) 0x420f40 ADD	X9, X17, X9

  (231) 0x420f44 ADD	X5, X17, X5

  (231) 0x420f48 LDR	X17, [X21, #16]

  (231) 0x420f4c SUB	X8, X14, #8

  (231) 0x420f50 ADD	X8, X4, X8

  (231) 0x420f54 ADD	X14, X4, X14

  (231) 0x420f58 ADD	X28, X30, X28,LSL #3

  (231) 0x420f5c ADD	X3, X17, X3,LSL #3

    (229) 0x420f60 LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

    (229) 0x420f64 LD1D	{Z1.D}, P0/Z, [X5, X0,LSL #3]

    (229) 0x420f68 LD1D	{Z2.D}, P0/Z, [X7, X0,LSL #3]

    (229) 0x420f6c LD1D	{Z6.D}, P0/Z, [X2, X0,LSL #3]

    (229) 0x420f70 LD1D	{Z4.D}, P0/Z, [X11, X0,LSL #3]

    (229) 0x420f74 LD1D	{Z7.D}, P0/Z, [X9, X0,LSL #3]

    (229) 0x420f78 LD1D	{Z16.D}, P0/Z, [X12, X0,LSL #3]

    (229) 0x420f7c LD1D	{Z18.D}, P0/Z, [X10, X0,LSL #3]

    (229) 0x420f80 FMUL	Z3.D, Z1.D, Z0.D

    (229) 0x420f84 FMUL	Z17.D, Z7.D, Z4.D

    (229) 0x420f88 FMAD	Z6.D, P1/M, Z2.D, Z3.D

    (229) 0x420f8c FMAD	Z18.D, P1/M, Z16.D, Z17.D

    (229) 0x420f90 FADD	Z19.D, Z6.D, Z18.D

    (229) 0x420f94 FMUL	Z20.D, Z19.D, Z5.D

    (229) 0x420f98 ST1D	{Z20.D}, P0, [X28, X0,LSL #3]

    (229) 0x420f9c LD1D	{Z21.D}, P0/Z, [X8, X0,LSL #3]

    (229) 0x420fa0 LD1D	{Z22.D}, P0/Z, [X14, X0,LSL #3]

    (229) 0x420fa4 FSUB	Z23.D, Z22.D, Z21.D

    (229) 0x420fa8 FADD	Z24.D, Z23.D, Z20.D

    (229) 0x420fac ST1D	{Z24.D}, P0, [X3, X0,LSL #3]

    (229) 0x420fb0 ADD	X0, X0, X15

    (229) 0x420fb4 WHILELO	P0.D, X0, X1

    (229) 0x420fb8 B.NE	420f60

  (231) 0x420fbc ADD	W16, W16, #1

  (231) 0x420fc0 ADD	X13, X13, #1

  (231) 0x420fc4 CMP	W19, W16

  (231) 0x420fc8 B.LE	421004

  (231) 0x420fcc SUB	W6, W27, W18

  (231) 0x420fd0 ORR	W1, WZR, W23

  (231) 0x420fd4 ORR	W12, WZR, W18

  (231) 0x420fd8 CMP	W6, W1

  (231) 0x420fdc CSEL	X1, X6, X1, #9

  (231) 0x420fe0 ADD	W18, W12, W1

  (231) 0x420fe4 ORR	W7, WZR, W22

  (231) 0x420fe8 CMP	W12, W18

  (231) 0x420fec B.CC	420eb0

  (232) 0x420ff0 ADD	W16, W16, #1

  (232) 0x420ff4 ORR	W18, WZR, W12

  (232) 0x420ff8 ADD	X13, X13, #1

  (232) 0x420ffc CMP	W19, W16

  (232) 0x421000 B.GT	420fcc

(230) 0x421004 LDP	X23, X24, [SP, #48]

(230) 0x421008 LDP	X25, X26, [SP, #64]

(230) 0x42100c LDP	X27, X28, [SP, #80]

(230) 0x421010 LDP	X19, X20, [SP, #16]

(230) 0x421014 LDP	X21, X22, [SP, #32]

(230) 0x421018 LDP	X29, X30, [SP], #112

(230) 0x42101c RET

  (228) 0x421020 LDP	X19, X20, [SP, #16]

  (228) 0x421024 LDP	X21, X22, [SP, #32]

  (228) 0x421028 LDP	X23, X24, [SP, #48]

  (228) 0x42102c LDP	X27, X28, [SP, #80]

  (228) 0x421030 LDP	X29, X30, [SP], #112

  (228) 0x421034 RET

  (228) 0x421038 ADD	W6, W6, #1

  (228) 0x42103c MOVZ	W4, #0

  (228) 0x421040 B	420e58

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.50 to 0.59 cycles (7.58x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00
cycles	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

4% of peak load performance is reached (4.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP W3, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W22, [X20, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W1, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421010 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W24, W19, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W28, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421020 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W23, W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W27, W24, W23, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W5, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W6, W27, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W4, W6, W21, W27	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 421038 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00
cycles	2.50	2.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

4% of peak load performance is reached (4.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP W3, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W22, [X20, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W1, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421010 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W24, W19, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W28, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421020 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W23, W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W27, W24, W23, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W5, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W6, W27, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W4, W6, W21, W27	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 421038 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.41	0.32
▼Loop 230 - advec_mom.cpp:95-100 - exec–	0	0
○Loop 228 - advec_mom.cpp:95-97 - exec	0	0
▼Loop 231 - advec_mom.cpp:97-100 - exec–	0	0
○Loop 229 - advec_mom.cpp:98-100 - exec	1.41	0.32
○Loop 232 - advec_mom.cpp:97-97 - exec	0	0

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