OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:62-66 [...]	Coverage: 1.13%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 62 - 66

--------------------------------------------------------------------------------

62: #pragma omp parallel for simd collapse(2)

63:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

64:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

0x420a6c STP	X29, X30, [SP, #944]!

0x420a70 ADD	X29, SP, #0

0x420a74 STP	X19, X20, [SP, #16]

0x420a78 STP	X25, X26, [SP, #64]

0x420a7c LDP	W25, W19, [X0, #40]

0x420a80 STP	X23, X24, [SP, #48]

0x420a84 ORR	X23, XZR, X0

0x420a88 LDR	W20, [X0, #32]

0x420a8c SUB	W25, W25, #1

0x420a90 ADD	W19, W19, #4

0x420a94 LDR	W0, [X0, #36]

0x420a98 CMP	W25, W19

0x420a9c B.GE	420c04

0x420aa0 SUB	W20, W20, #1

0x420aa4 STP	X21, X22, [SP, #32]

0x420aa8 ADD	W22, W0, #4

0x420aac SUB	W26, W19, W25

0x420ab0 CMP	W20, W22

0x420ab4 B.GE	420c00

0x420ab8 SUB	W21, W22, W20

0x420abc BL	403530

0x420ac0 MADD	W26, W26, W21, WZR

0x420ac4 ORR	W24, WZR, W0

0x420ac8 BL	4033c0

0x420acc ORR	W2, WZR, W0

0x420ad0 UDIV	W1, W26, W24

0x420ad4 MSUB	W3, W1, W24, W26

0x420ad8 CMP	W0, W3

0x420adc B.CC	420c18

(220) 0x420ae0 MADD	W16, W1, W2, W3

(220) 0x420ae4 ADD	W13, W1, W16

(220) 0x420ae8 CMP	W16, W13

(220) 0x420aec B.CS	420c00

(220) 0x420af0 UDIV	W4, W16, W21

(220) 0x420af4 MOVZ	W14, #0

(220) 0x420af8 CNTD	X8, ALL

(220) 0x420afc LDP	X12, X11, [X23]

(220) 0x420b00 LDP	X10, X9, [X23, #16]

(220) 0x420b04 MSUB	W7, W4, W21, W16

(220) 0x420b08 ADD	W5, W4, W25

(220) 0x420b0c SBFM	X17, X5, #0, #31

(220) 0x420b10 ADD	W2, W7, W20

(220) 0x420b14 SUB	W15, W22, W2

(220) 0x420b18 CMP	W1, W15

(220) 0x420b1c CSEL	X30, X1, X15, #9

(220) 0x420b20 ADD	W15, W16, W30

(220) 0x420b24 CMP	W16, W15

(220) 0x420b28 B.CS	420be8

  (222) 0x420b2c LDR	X24, [X11]

  (222) 0x420b30 SBFM	X23, X2, #0, #31

  (222) 0x420b34 ADD	X16, X17, #1

  (222) 0x420b38 MOVZ	X0, #0

  (222) 0x420b3c WHILELO	P0.D, XZR, X30

  (222) 0x420b40 LDR	X6, [X9]

  (222) 0x420b44 LDR	X18, [X10]

  (222) 0x420b48 MADD	X2, X17, X24, X23

  (222) 0x420b4c LDR	X3, [X12]

  (222) 0x420b50 MADD	X25, X17, X6, X23

  (222) 0x420b54 LDR	X22, [X11, #16]

  (222) 0x420b58 MADD	X26, X17, X18, X23

  (222) 0x420b5c LDR	X7, [X12, #16]

  (222) 0x420b60 MADD	X17, X17, X3, X3

  (222) 0x420b64 LDR	X24, [X9, #16]

  (222) 0x420b68 ADD	X1, X22, X2,LSL #3

  (222) 0x420b6c LDR	X22, [X10, #16]

  (222) 0x420b70 SUB	X4, X17, X3

  (222) 0x420b74 ADD	X5, X17, X23

  (222) 0x420b78 ADD	X23, X4, X23

  (222) 0x420b7c ADD	X18, X7, X5,LSL #3

  (222) 0x420b80 ADD	X6, X7, X23,LSL #3

  (222) 0x420b84 ADD	X25, X24, X25,LSL #3

  (222) 0x420b88 ADD	X26, X22, X26,LSL #3

    (221) 0x420b8c LD1D	{Z1.D}, P0/Z, [X1, X0,LSL #3]

    (221) 0x420b90 ST1D	{Z1.D}, P0, [X25, X0,LSL #3]

    (221) 0x420b94 LD1D	{Z0.D}, P0/Z, [X18, X0,LSL #3]

    (221) 0x420b98 LD1D	{Z2.D}, P0/Z, [X6, X0,LSL #3]

    (221) 0x420b9c FADD	Z3.D, Z0.D, Z1.D

    (221) 0x420ba0 FSUB	Z4.D, Z3.D, Z2.D

    (221) 0x420ba4 ST1D	{Z4.D}, P0, [X26, X0,LSL #3]

    (221) 0x420ba8 ADD	X0, X0, X8

    (221) 0x420bac WHILELO	P0.D, X0, X30

    (221) 0x420bb0 B.NE	420b8c

  (222) 0x420bb4 ADD	W30, W14, W16

  (222) 0x420bb8 ORR	X17, XZR, X16

  (222) 0x420bbc CMP	W19, W30

  (222) 0x420bc0 B.LE	420c00

  (222) 0x420bc4 SUB	W1, W13, W15

  (222) 0x420bc8 ORR	W16, WZR, W15

  (222) 0x420bcc ORR	W15, WZR, W21

  (222) 0x420bd0 ORR	W2, WZR, W20

  (222) 0x420bd4 CMP	W1, W15

  (222) 0x420bd8 CSEL	X30, X1, X15, #9

  (222) 0x420bdc ADD	W15, W16, W30

  (222) 0x420be0 CMP	W16, W15

  (222) 0x420be4 B.CC	420b2c

  (223) 0x420be8 ORR	W15, WZR, W16

  (223) 0x420bec ADD	X16, X17, #1

  (223) 0x420bf0 ADD	W30, W14, W16

  (223) 0x420bf4 ORR	X17, XZR, X16

  (223) 0x420bf8 CMP	W19, W30

  (223) 0x420bfc B.GT	420bc4

(220) 0x420c00 LDP	X21, X22, [SP, #32]

(220) 0x420c04 LDP	X19, X20, [SP, #16]

(220) 0x420c08 LDP	X23, X24, [SP, #48]

(220) 0x420c0c LDP	X25, X26, [SP, #64]

(220) 0x420c10 LDP	X29, X30, [SP], #80

(220) 0x420c14 RET

(220) 0x420c18 ADD	W1, W1, #1

(220) 0x420c1c MOVZ	W3, #0

(220) 0x420c20 B	420ae0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:62-66

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420a6c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420c04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420c00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 420c18 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:62-66

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420a6c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420c04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420c00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 420c18 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.13	0.26
▼Loop 220 - advec_mom.cpp:62-66 - exec–	0	0
▼Loop 222 - advec_mom.cpp:64-66 - exec–	0.02	0
○Loop 221 - advec_mom.cpp:65-66 - exec	1.11	0.25
○Loop 223 - advec_mom.cpp:66-66 - exec	0	0

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Vectorization

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code