OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:53-57 [...]	Coverage: 1.11%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 53 - 57

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

0x420870 STP	X29, X30, [SP, #944]!

0x420874 ADD	X29, SP, #0

0x420878 STP	X19, X20, [SP, #16]

0x42087c STP	X25, X26, [SP, #64]

0x420880 LDP	W25, W19, [X0, #48]

0x420884 LDP	W20, W3, [X0, #40]

0x420888 SUB	W25, W25, #1

0x42088c ADD	W19, W19, #4

0x420890 CMP	W25, W19

0x420894 B.GE	420a48

0x420898 SUB	W20, W20, #1

0x42089c STP	X21, X22, [SP, #32]

0x4208a0 ADD	W22, W3, #4

0x4208a4 SUB	W26, W19, W25

0x4208a8 CMP	W20, W22

0x4208ac B.GE	420a64

0x4208b0 SUB	W21, W22, W20

0x4208b4 STP	X23, X24, [SP, #48]

0x4208b8 ORR	X23, XZR, X0

0x4208bc MADD	W26, W26, W21, WZR

0x4208c0 BL	403530

0x4208c4 ORR	W24, WZR, W0

0x4208c8 BL	4033c0

0x4208cc UDIV	W1, W26, W24

0x4208d0 ORR	W2, WZR, W0

0x4208d4 MSUB	W0, W1, W24, W26

0x4208d8 CMP	W2, W0

0x4208dc B.CC	420a58

(216) 0x4208e0 MADD	W18, W1, W2, W0

(216) 0x4208e4 ADD	W15, W1, W18

(216) 0x4208e8 CMP	W18, W15

(216) 0x4208ec B.CS	420a40

(216) 0x4208f0 UDIV	W4, W18, W21

(216) 0x4208f4 MOVZ	W16, #0

(216) 0x4208f8 CNTD	X9, ALL

(216) 0x4208fc LDP	X14, X13, [X23]

(216) 0x420900 LDP	X12, X11, [X23, #16]

(216) 0x420904 LDR	X10, [X23, #32]

(216) 0x420908 MSUB	W5, W4, W21, W18

(216) 0x42090c ADD	W6, W4, W25

(216) 0x420910 SBFM	X30, X6, #0, #31

(216) 0x420914 ADD	W4, W5, W20

(216) 0x420918 SUB	W17, W22, W4

(216) 0x42091c CMP	W1, W17

(216) 0x420920 CSEL	X25, X1, X17, #9

(216) 0x420924 ADD	W17, W18, W25

(216) 0x420928 CMP	W18, W17

(216) 0x42092c B.CS	420a1c

  (218) 0x420930 LDR	X2, [X13]

  (218) 0x420934 SBFM	X22, X4, #0, #31

  (218) 0x420938 ADD	X18, X30, #1

  (218) 0x42093c ADD	X8, X22, #1

  (218) 0x420940 MOVZ	X0, #0

  (218) 0x420944 WHILELO	P0.D, XZR, X25

  (218) 0x420948 LDR	X23, [X11]

  (218) 0x42094c LDR	X24, [X12]

  (218) 0x420950 MADD	X5, X30, X2, X2

  (218) 0x420954 LDR	X7, [X10]

  (218) 0x420958 MADD	X26, X30, X23, X22

  (218) 0x42095c SUB	X4, X5, X2

  (218) 0x420960 LDR	X2, [X14]

  (218) 0x420964 ADD	X6, X5, X22

  (218) 0x420968 MADD	X1, X30, X24, X22

  (218) 0x42096c LDR	X23, [X13, #16]

  (218) 0x420970 MADD	X3, X30, X7, X22

  (218) 0x420974 ADD	X7, X4, X22

  (218) 0x420978 LDR	X24, [X11, #16]

  (218) 0x42097c MADD	X30, X30, X2, XZR

  (218) 0x420980 LDR	X2, [X12, #16]

  (218) 0x420984 ADD	X5, X23, X6,LSL #3

  (218) 0x420988 LDR	X6, [X14, #16]

  (218) 0x42098c ADD	X8, X8, X30

  (218) 0x420990 ADD	X22, X30, X22

  (218) 0x420994 ADD	X26, X24, X26,LSL #3

  (218) 0x420998 LDR	X24, [X10, #16]

  (218) 0x42099c ADD	X4, X23, X7,LSL #3

  (218) 0x4209a0 ADD	X1, X2, X1,LSL #3

  (218) 0x4209a4 ADD	X23, X6, X8,LSL #3

  (218) 0x4209a8 ADD	X7, X6, X22,LSL #3

  (218) 0x4209ac ADD	X3, X24, X3,LSL #3

    (217) 0x4209b0 LD1D	{Z2.D}, P0/Z, [X1, X0,LSL #3]

    (217) 0x4209b4 LD1D	{Z0.D}, P0/Z, [X23, X0,LSL #3]

    (217) 0x4209b8 LD1D	{Z1.D}, P0/Z, [X7, X0,LSL #3]

    (217) 0x4209bc FADD	Z3.D, Z0.D, Z2.D

    (217) 0x4209c0 FSUB	Z4.D, Z3.D, Z1.D

    (217) 0x4209c4 ST1D	{Z4.D}, P0, [X3, X0,LSL #3]

    (217) 0x4209c8 LD1D	{Z5.D}, P0/Z, [X5, X0,LSL #3]

    (217) 0x4209cc LD1D	{Z6.D}, P0/Z, [X4, X0,LSL #3]

    (217) 0x4209d0 FSUB	Z7.D, Z5.D, Z6.D

    (217) 0x4209d4 FADD	Z16.D, Z7.D, Z4.D

    (217) 0x4209d8 ST1D	{Z16.D}, P0, [X26, X0,LSL #3]

    (217) 0x4209dc ADD	X0, X0, X9

    (217) 0x4209e0 WHILELO	P0.D, X0, X25

    (217) 0x4209e4 B.NE	4209b0

  (218) 0x4209e8 ADD	W25, W16, W18

  (218) 0x4209ec ORR	X30, XZR, X18

  (218) 0x4209f0 CMP	W19, W25

  (218) 0x4209f4 B.LE	420a40

  (218) 0x4209f8 SUB	W1, W15, W17

  (218) 0x4209fc ORR	W18, WZR, W17

  (218) 0x420a00 ORR	W17, WZR, W21

  (218) 0x420a04 ORR	W4, WZR, W20

  (218) 0x420a08 CMP	W1, W17

  (218) 0x420a0c CSEL	X25, X1, X17, #9

  (218) 0x420a10 ADD	W17, W18, W25

  (218) 0x420a14 CMP	W18, W17

  (218) 0x420a18 B.CC	420930

  (219) 0x420a1c ORR	W17, WZR, W18

  (219) 0x420a20 ADD	X18, X30, #1

  (219) 0x420a24 ADD	W25, W16, W18

  (219) 0x420a28 ORR	X30, XZR, X18

  (219) 0x420a2c CMP	W19, W25

  (219) 0x420a30 B.GT	4209f8

(216) 0x420a34 HINT	#0

(216) 0x420a38 HINT	#0

(216) 0x420a3c HINT	#0

(216) 0x420a40 LDP	X21, X22, [SP, #32]

(216) 0x420a44 LDP	X23, X24, [SP, #48]

(216) 0x420a48 LDP	X19, X20, [SP, #16]

(216) 0x420a4c LDP	X25, X26, [SP, #64]

(216) 0x420a50 LDP	X29, X30, [SP], #80

(216) 0x420a54 RET

(216) 0x420a58 ADD	W1, W1, #1

(216) 0x420a5c MOVZ	W0, #0

(216) 0x420a60 B	4208e0

0x420a64 LDP	X21, X22, [SP, #32]

0x420a68 B	420a48

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:53-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420870

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420a48 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420a64 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 420a58 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 420a48 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:53-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420870

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420a48 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420a64 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 420a58 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 420a48 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.11	0.25
▼Loop 216 - advec_mom.cpp:53-57 - exec–	0	0
▼Loop 218 - advec_mom.cpp:55-57 - exec–	0	0
○Loop 217 - advec_mom.cpp:56-57 - exec	1.11	0.25
○Loop 219 - advec_mom.cpp:57-57 - exec	0	0

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code