OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-48 [...]	Coverage: 1.33%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x420680 STP	X29, X30, [SP, #944]!

0x420684 ADD	X29, SP, #0

0x420688 STP	X19, X20, [SP, #16]

0x42068c STP	X25, X26, [SP, #64]

0x420690 LDP	W25, W19, [X0, #48]

0x420694 LDP	W20, W3, [X0, #40]

0x420698 SUB	W25, W25, #1

0x42069c ADD	W19, W19, #4

0x4206a0 CMP	W25, W19

0x4206a4 B.GE	42084c

0x4206a8 SUB	W20, W20, #1

0x4206ac STP	X21, X22, [SP, #32]

0x4206b0 ADD	W22, W3, #4

0x4206b4 SUB	W26, W19, W25

0x4206b8 CMP	W20, W22

0x4206bc B.GE	420868

0x4206c0 SUB	W21, W22, W20

0x4206c4 STP	X23, X24, [SP, #48]

0x4206c8 ORR	X23, XZR, X0

0x4206cc MADD	W26, W26, W21, WZR

0x4206d0 BL	403530

0x4206d4 ORR	W24, WZR, W0

0x4206d8 BL	4033c0

0x4206dc UDIV	W1, W26, W24

0x4206e0 ORR	W2, WZR, W0

0x4206e4 MSUB	W0, W1, W24, W26

0x4206e8 CMP	W2, W0

0x4206ec B.CC	42085c

(212) 0x4206f0 MADD	W18, W1, W2, W0

(212) 0x4206f4 ADD	W15, W1, W18

(212) 0x4206f8 CMP	W18, W15

(212) 0x4206fc B.CS	420844

(212) 0x420700 UDIV	W4, W18, W21

(212) 0x420704 MOVZ	W16, #0

(212) 0x420708 CNTD	X9, ALL

(212) 0x42070c LDP	X14, X13, [X23]

(212) 0x420710 LDP	X12, X11, [X23, #16]

(212) 0x420714 LDR	X10, [X23, #32]

(212) 0x420718 MSUB	W5, W4, W21, W18

(212) 0x42071c ADD	W6, W4, W25

(212) 0x420720 SBFM	X30, X6, #0, #31

(212) 0x420724 ADD	W4, W5, W20

(212) 0x420728 SUB	W17, W22, W4

(212) 0x42072c CMP	W1, W17

(212) 0x420730 CSEL	X25, X1, X17, #9

(212) 0x420734 ADD	W17, W18, W25

(212) 0x420738 CMP	W18, W17

(212) 0x42073c B.CS	42082c

  (214) 0x420740 LDR	X2, [X13]

  (214) 0x420744 SBFM	X22, X4, #0, #31

  (214) 0x420748 ADD	X18, X30, #1

  (214) 0x42074c ADD	X8, X22, #1

  (214) 0x420750 MOVZ	X0, #0

  (214) 0x420754 WHILELO	P0.D, XZR, X25

  (214) 0x420758 LDR	X23, [X11]

  (214) 0x42075c LDR	X24, [X12]

  (214) 0x420760 MADD	X5, X30, X2, X2

  (214) 0x420764 LDR	X7, [X10]

  (214) 0x420768 MADD	X26, X30, X23, X22

  (214) 0x42076c SUB	X4, X5, X2

  (214) 0x420770 LDR	X2, [X14]

  (214) 0x420774 ADD	X6, X5, X22

  (214) 0x420778 MADD	X1, X30, X24, X22

  (214) 0x42077c LDR	X23, [X13, #16]

  (214) 0x420780 MADD	X3, X30, X7, X22

  (214) 0x420784 ADD	X7, X4, X22

  (214) 0x420788 LDR	X24, [X11, #16]

  (214) 0x42078c MADD	X30, X30, X2, XZR

  (214) 0x420790 LDR	X2, [X12, #16]

  (214) 0x420794 ADD	X5, X23, X6,LSL #3

  (214) 0x420798 LDR	X6, [X14, #16]

  (214) 0x42079c ADD	X8, X8, X30

  (214) 0x4207a0 ADD	X22, X30, X22

  (214) 0x4207a4 ADD	X26, X24, X26,LSL #3

  (214) 0x4207a8 LDR	X24, [X10, #16]

  (214) 0x4207ac ADD	X4, X23, X7,LSL #3

  (214) 0x4207b0 ADD	X1, X2, X1,LSL #3

  (214) 0x4207b4 ADD	X23, X6, X8,LSL #3

  (214) 0x4207b8 ADD	X7, X6, X22,LSL #3

  (214) 0x4207bc ADD	X3, X24, X3,LSL #3

    (213) 0x4207c0 LD1D	{Z2.D}, P0/Z, [X1, X0,LSL #3]

    (213) 0x4207c4 LD1D	{Z0.D}, P0/Z, [X5, X0,LSL #3]

    (213) 0x4207c8 LD1D	{Z1.D}, P0/Z, [X4, X0,LSL #3]

    (213) 0x4207cc FADD	Z3.D, Z0.D, Z2.D

    (213) 0x4207d0 FSUB	Z4.D, Z3.D, Z1.D

    (213) 0x4207d4 ST1D	{Z4.D}, P0, [X3, X0,LSL #3]

    (213) 0x4207d8 LD1D	{Z5.D}, P0/Z, [X23, X0,LSL #3]

    (213) 0x4207dc LD1D	{Z6.D}, P0/Z, [X7, X0,LSL #3]

    (213) 0x4207e0 FSUB	Z7.D, Z5.D, Z6.D

    (213) 0x4207e4 FADD	Z16.D, Z7.D, Z4.D

    (213) 0x4207e8 ST1D	{Z16.D}, P0, [X26, X0,LSL #3]

    (213) 0x4207ec ADD	X0, X0, X9

    (213) 0x4207f0 WHILELO	P0.D, X0, X25

    (213) 0x4207f4 B.NE	4207c0

  (214) 0x4207f8 ADD	W25, W16, W18

  (214) 0x4207fc ORR	X30, XZR, X18

  (214) 0x420800 CMP	W19, W25

  (214) 0x420804 B.LE	420844

  (214) 0x420808 SUB	W1, W15, W17

  (214) 0x42080c ORR	W18, WZR, W17

  (214) 0x420810 ORR	W17, WZR, W21

  (214) 0x420814 ORR	W4, WZR, W20

  (214) 0x420818 CMP	W1, W17

  (214) 0x42081c CSEL	X25, X1, X17, #9

  (214) 0x420820 ADD	W17, W18, W25

  (214) 0x420824 CMP	W18, W17

  (214) 0x420828 B.CC	420740

  (215) 0x42082c ORR	W17, WZR, W18

  (215) 0x420830 ADD	X18, X30, #1

  (215) 0x420834 ADD	W25, W16, W18

  (215) 0x420838 ORR	X30, XZR, X18

  (215) 0x42083c CMP	W19, W25

  (215) 0x420840 B.GT	420808

(212) 0x420844 LDP	X21, X22, [SP, #32]

(212) 0x420848 LDP	X23, X24, [SP, #48]

(212) 0x42084c LDP	X19, X20, [SP, #16]

(212) 0x420850 LDP	X25, X26, [SP, #64]

(212) 0x420854 LDP	X29, X30, [SP], #80

(212) 0x420858 RET

(212) 0x42085c ADD	W1, W1, #1

(212) 0x420860 MOVZ	W0, #0

(212) 0x420864 B	4206f0

0x420868 LDP	X21, X22, [SP, #32]

0x42086c B	42084c

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 42084c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420868 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42085c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 42084c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 42084c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420868 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42085c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 42084c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.33	0.3
▼Loop 212 - advec_mom.cpp:44-48 - exec–	0	0
▼Loop 214 - advec_mom.cpp:46-48 - exec–	0	0
○Loop 213 - advec_mom.cpp:47-48 - exec	1.33	0.3
○Loop 215 - advec_mom.cpp:48-48 - exec	0	0

Report Configuration

Vectorization

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code