OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage: 7.46%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

[...]

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

0x420010 STP	X29, X30, [SP, #864]!

0x420014 ADD	X29, SP, #0

0x420018 STP	X21, X22, [SP, #32]

0x42001c ORR	X21, XZR, X0

0x420020 STP	X23, X24, [SP, #48]

0x420024 LDP	W22, W24, [X0, #64]

0x420028 LDR	W0, [X0, #56]

0x42002c LDR	W1, [X21, #60]

0x420030 ADD	W2, W24, #4

0x420034 ADD	W22, W22, #1

0x420038 ADD	W3, W0, #1

0x42003c STP	W2, W3, [SP, #112]

0x420040 CMP	W22, W2

0x420044 B.GE	4202f4

0x420048 STP	X19, X20, [SP, #16]

0x42004c ADD	W20, W1, #2

0x420050 SUB	W23, W2, W22

0x420054 CMP	W3, W20

0x420058 B.GE	4202f0

0x42005c SUB	W4, W20, W3

0x420060 MADD	W23, W23, W4, WZR

0x420064 STR	W4, [SP, #120]

0x420068 BL	403530

0x42006c ORR	W19, WZR, W0

0x420070 BL	4033c0

0x420074 UDIV	W6, W23, W19

0x420078 ORR	W5, WZR, W0

0x42007c MSUB	W7, W6, W19, W23

0x420080 CMP	W0, W7

0x420084 B.CC	42035c

  (208) 0x420088 MADD	W5, W6, W5, W7

  (208) 0x42008c ADD	W8, W6, W5

  (208) 0x420090 STR	W8, [SP, #124]

  (208) 0x420094 CMP	W5, W8

  (208) 0x420098 B.CS	4202f0

  (208) 0x42009c LDR	W10, [SP, #120]

  (208) 0x4200a0 ORR	X9, XZR, #3840

  (208) 0x4200a4 FMOV	D7, #1.0000000

  (208) 0x4200a8 MOVK	X9, #16325

  (208) 0x4200ac LDP	X14, X15, [X21]

  (208) 0x4200b0 FMOV	D18, #2.0000000

  (208) 0x4200b4 FMOV	D16, #-1.0000000

  (208) 0x4200b8 ADD	W24, W24, #2

  (208) 0x4200bc FMOV	D17, X9

  (208) 0x4200c0 UDIV	W11, W5, W10

  (208) 0x4200c4 LDR	W18, [SP, #116]

  (208) 0x4200c8 STP	X25, X26, [SP, #64]

  (208) 0x4200cc STP	X27, X28, [SP, #80]

  (208) 0x4200d0 LDR	X16, [X21, #16]

  (208) 0x4200d4 LDP	X28, X27, [X21, #24]

  (208) 0x4200d8 MSUB	W12, W11, W10, W5

  (208) 0x4200dc ADD	W19, W11, W22

  (208) 0x4200e0 SBFM	X13, X19, #0, #31

  (208) 0x4200e4 SUB	W25, W19, #2

  (208) 0x4200e8 STP	X14, X15, [SP, #136]

  (208) 0x4200ec SUB	X11, X13, #1

  (208) 0x4200f0 ADD	W18, W12, W18

  (208) 0x4200f4 LDR	X17, [X21, #40]

  (208) 0x4200f8 SUB	W14, W20, W18

  (208) 0x4200fc STR	X16, [SP, #152]

  (208) 0x420100 LDR	X26, [X21, #48]

  (208) 0x420104 STR	X17, [SP, #128]

  (208) 0x420108 CMP	W6, W14

  (208) 0x42010c CSEL	W30, W6, W14, #9

  (208) 0x420110 ADD	W21, W5, W30

  (208) 0x420114 ADD	W19, W19, #1

  (208) 0x420118 STR	W21, [SP, #108]

  (208) 0x42011c CMP	W5, W21

  (208) 0x420120 B.CS	420318

      (209) 0x420124 LDR	X23, [X28]

      (209) 0x420128 SBFM	X0, X18, #0, #31

      (209) 0x42012c SUB	W22, W30, #1

      (209) 0x420130 LDP	X9, X8, [SP, #128]

      (209) 0x420134 ADD	X5, X0, #1

      (209) 0x420138 SBFM	X30, X25, #0, #31

      (209) 0x42013c ADD	X12, X5, X22

      (209) 0x420140 LDR	X1, [X27]

      (209) 0x420144 MADD	X7, X13, X23, XZR

      (209) 0x420148 LDR	X2, [X26]

      (209) 0x42014c LDR	X6, [X28, #16]

      (209) 0x420150 MADD	X4, X13, X1, XZR

      (209) 0x420154 LDR	X3, [X27, #16]

      (209) 0x420158 MADD	X20, X13, X2, XZR

      (209) 0x42015c LDR	X10, [SP, #144]

      (209) 0x420160 ADD	X17, X6, X7,LSL #3

      (209) 0x420164 LDR	X16, [SP, #152]

      (209) 0x420168 ADD	X18, X3, X4,LSL #3

      (209) 0x42016c LDR	X21, [X8, #8]

      (209) 0x420170 LDR	X15, [X26, #16]

      (209) 0x420174 LDR	X8, [X10]

      (209) 0x420178 ADD	X23, X21, X13,LSL #3

      (209) 0x42017c LDR	X22, [X9]

      (209) 0x420180 ADD	X20, X15, X20,LSL #3

      (209) 0x420184 LDR	X7, [X16]

      (209) 0x420188 LDR	X4, [X10, #16]

      (209) 0x42018c LDR	X14, [X9, #16]

      (209) 0x420190 LDR	X6, [X16, #16]

      (209) 0x420194 HINT	#0

      (209) 0x420198 HINT	#0

      (209) 0x42019c HINT	#0

      (209) 0x4201a0 ORR	X1, XZR, X11

      (209) 0x4201a4 ORR	X2, XZR, X30

      (209) 0x4201a8 LDR	D6, [X18, X0,LSL #3]

      (209) 0x4201ac ORR	X3, XZR, X13

      (209) 0x4201b0 ORR	X10, XZR, X11

      (209) 0x4201b4 FCMPE	D6, #0

      (209) 0x4201b8 B.GT	4201d4

    (210) 0x4201bc CMP	W24, W19

    (210) 0x4201c0 CSEL	W2, W24, W19, #13

    (210) 0x4201c4 SBFM	X10, X2, #0, #31

    (210) 0x4201c8 ORR	X3, XZR, X11

    (210) 0x4201cc ORR	X1, XZR, X13

    (210) 0x4201d0 ORR	X2, XZR, X10

    (210) 0x4201d4 MADD	X9, X22, X1, X0

    (210) 0x4201d8 FABS	D2, D6

    (210) 0x4201dc LDR	D4, [X21, X10,LSL #3]

    (210) 0x4201e0 MADD	X16, X8, X3, X0

    (210) 0x4201e4 MADD	X10, X8, X1, X0

    (210) 0x4201e8 LDR	D5, [X23]

    (210) 0x4201ec MADD	X15, X8, X2, X0

    (210) 0x4201f0 LDR	D1, [X14, X9,LSL #3]

    (210) 0x4201f4 MADD	X1, X7, X1, X0

    (210) 0x4201f8 MADD	X3, X7, X3, X0

    (210) 0x4201fc LDR	D0, [X4, X10,LSL #3]

    (210) 0x420200 MADD	X2, X7, X2, X0

    (210) 0x420204 LDR	D3, [X4, X16,LSL #3]

    (210) 0x420208 FDIV	D26, D5, D4

    (210) 0x42020c LDR	D19, [X4, X15,LSL #3]

    (210) 0x420210 FDIV	D23, D2, D1

    (210) 0x420214 FSUB	D24, D3, S0

    (210) 0x420218 FSUB	D27, D0, S19

    (210) 0x42021c FCMPE	D24, #0

    (210) 0x420220 FABS	D25, D24

    (210) 0x420224 FMUL	D29, D24, D27

    (210) 0x420228 FABS	D28, D27

    (210) 0x42022c FMINNM	D22, D25, D28

    (210) 0x420230 FCSEL	D20, D16, D7, #9

    (210) 0x420234 FCMPE	D29, #0

    (210) 0x420238 FADD	D30, D23, D7

    (210) 0x42023c FSUB	D21, D7, S23

    (210) 0x420240 FSUB	D31, D18, S23

    (210) 0x420244 FMUL	D24, D26, D30

    (210) 0x420248 B.LS	420264

    (210) 0x42024c FMUL	D2, D25, D31

    (210) 0x420250 FMADD	D4, D28, D24, D2

    (210) 0x420254 FMUL	D1, D4, D17

    (210) 0x420258 FMINNM	D3, D1, D22

    (210) 0x42025c FMUL	D23, D3, D21

    (210) 0x420260 FMADD	D0, D23, D20, D0

    (210) 0x420264 FMUL	D25, D0, D6

    (210) 0x420268 STR	D25, [X17, X0,LSL #3]

    (210) 0x42026c FABS	D6, D25

    (210) 0x420270 LDR	D5, [X6, X1,LSL #3]

    (210) 0x420274 LDR	D21, [X6, X3,LSL #3]

    (210) 0x420278 LDR	D26, [X6, X2,LSL #3]

    (210) 0x42027c LDR	D20, [X4, X10,LSL #3]

    (210) 0x420280 FMUL	D27, D5, D25

    (210) 0x420284 FSUB	D28, D21, S5

    (210) 0x420288 LDR	D22, [X14, X9,LSL #3]

    (210) 0x42028c FSUB	D19, D5, S26

    (210) 0x420290 FABS	D30, D28

    (210) 0x420294 FCMPE	D28, #0

    (210) 0x420298 FMUL	D29, D22, D20

    (210) 0x42029c FMUL	D2, D28, D19

    (210) 0x4202a0 FABS	D4, D19

    (210) 0x4202a4 FMINNM	D23, D30, D4

    (210) 0x4202a8 FMUL	D31, D30, D31

    (210) 0x4202ac FCSEL	D3, D16, D7, #9

    (210) 0x4202b0 FCMPE	D2, #0

    (210) 0x4202b4 FMADD	D24, D4, D24, D31

    (210) 0x4202b8 B.LS	420304

    (210) 0x4202bc FDIV	D0, D6, D29

    (210) 0x4202c0 FMUL	D1, D24, D17

    (210) 0x4202c4 FMINNM	D21, D1, D23

    (210) 0x4202c8 FSUB	D6, D7, S0

    (210) 0x4202cc FMUL	D26, D6, D21

    (210) 0x4202d0 FMADD	D5, D26, D3, D5

    (210) 0x4202d4 FMUL	D25, D5, D25

    (210) 0x4202d8 STR	D25, [X20, X0,LSL #3]

    (210) 0x4202dc ORR	X0, XZR, X5

    (210) 0x4202e0 CMP	X12, X5

    (210) 0x4202e4 B.EQ	420314

    (210) 0x4202e8 ADD	X5, X5, #1

    (210) 0x4202ec B	4201a0

(207) 0x4202f0 LDP	X19, X20, [SP, #16]

(207) 0x4202f4 LDP	X21, X22, [SP, #32]

(207) 0x4202f8 LDP	X23, X24, [SP, #48]

(207) 0x4202fc LDP	X29, X30, [SP], #160

(207) 0x420300 RET

  (206) 0x420304 STR	D27, [X20, X0,LSL #3]

  (206) 0x420308 ORR	X0, XZR, X5

  (206) 0x42030c CMP	X12, X5

  (206) 0x420310 B.NE	4202e8

(207) 0x420314 LDR	W5, [SP, #108]

  (208) 0x420318 ADD	X11, X11, #1

  (208) 0x42031c ADD	X13, X13, #1

  (208) 0x420320 LDR	W12, [SP, #112]

  (208) 0x420324 ADD	W25, W25, #1

  (208) 0x420328 CMP	W12, W19

  (208) 0x42032c B.LE	420340

  (208) 0x420330 LDP	W14, W17, [SP, #120]

  (208) 0x420334 LDR	W18, [SP, #116]

  (208) 0x420338 SUB	W6, W17, W5

  (208) 0x42033c B	420108

  (208) 0x420340 LDP	X19, X20, [SP, #16]

  (208) 0x420344 LDP	X21, X22, [SP, #32]

  (208) 0x420348 LDP	X23, X24, [SP, #48]

  (208) 0x42034c LDP	X25, X26, [SP, #64]

  (208) 0x420350 LDP	X27, X28, [SP, #80]

  (208) 0x420354 LDP	X29, X30, [SP], #160

  (208) 0x420358 RET

  (208) 0x42035c ADD	W6, W6, #1

  (208) 0x420360 MOVZ	W7, #0

  (208) 0x420364 B	420088

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:157-163,169-202

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.62 cycles (7.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W24, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X21, #60]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W24, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP W2, W3, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4202f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W20, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W23, W2, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4202f0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W4, W20, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W23, W23, W4, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR W4, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W6, W23, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W7, W6, W19, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42035c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:157-163,169-202

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W24, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X21, #60]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W24, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP W2, W3, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4202f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W20, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W23, W2, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4202f0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W4, W20, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W23, W23, W4, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR W4, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W6, W23, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W7, W6, W19, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42035c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	7.46	1.71
▼Loop 207 - advec_cell.cpp:157-202 - exec–	0	0
▼Loop 206 - advec_cell.cpp:163-202 - exec–	1.68	0.38
▼Loop 210 - advec_cell.cpp:163-202 - exec–	5.42	1.24
○Loop 209 - advec_cell.cpp:163-179 - exec	0.37	0.09
○Loop 208 - advec_cell.cpp:157-202 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code