OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:65-110 [...]	Coverage: 6.86%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 65 - 110

--------------------------------------------------------------------------------

65: #pragma omp parallel for simd collapse(2)

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

[...]

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

0x41fce0 STP	X29, X30, [SP, #896]!

0x41fce4 ADD	X29, SP, #0

0x41fce8 STP	X21, X22, [SP, #32]

0x41fcec STP	X23, X24, [SP, #48]

0x41fcf0 ORR	X23, XZR, X0

0x41fcf4 LDP	W24, W22, [X0, #64]

0x41fcf8 STP	X19, X20, [SP, #16]

0x41fcfc LDR	W0, [X0, #56]

0x41fd00 ADD	W24, W24, #1

0x41fd04 ADD	W22, W22, #2

0x41fd08 LDR	W20, [X23, #60]

0x41fd0c ADD	W1, W0, #1

0x41fd10 STR	W1, [SP, #108]

0x41fd14 CMP	W24, W22

0x41fd18 B.GE	41ffa0

0x41fd1c ADD	W21, W20, #4

0x41fd20 STP	X25, X26, [SP, #64]

0x41fd24 SUB	W25, W22, W24

0x41fd28 CMP	W1, W21

0x41fd2c B.GE	41ff9c

0x41fd30 SUB	W2, W21, W1

0x41fd34 MADD	W26, W25, W2, WZR

0x41fd38 STR	W2, [SP, #112]

0x41fd3c BL	403530

0x41fd40 ORR	W19, WZR, W0

0x41fd44 BL	4033c0

0x41fd48 UDIV	W3, W26, W19

0x41fd4c ORR	W4, WZR, W0

0x41fd50 MSUB	W5, W3, W19, W26

0x41fd54 CMP	W0, W5

0x41fd58 B.CC	420004

  (203) 0x41fd5c MADD	W5, W3, W4, W5

  (203) 0x41fd60 ADD	W6, W3, W5

  (203) 0x41fd64 STR	W6, [SP, #116]

  (203) 0x41fd68 CMP	W5, W6

  (203) 0x41fd6c B.CS	41ff9c

  (203) 0x41fd70 LDR	W8, [SP, #112]

  (203) 0x41fd74 ORR	X7, XZR, #3840

  (203) 0x41fd78 FMOV	D7, #1.0000000

  (203) 0x41fd7c MOVK	X7, #16325

  (203) 0x41fd80 STP	X27, X28, [SP, #80]

  (203) 0x41fd84 FMOV	D18, #2.0000000

  (203) 0x41fd88 FMOV	D16, #-1.0000000

  (203) 0x41fd8c ADD	W20, W20, #2

  (203) 0x41fd90 FMOV	D17, X7

  (203) 0x41fd94 UDIV	W9, W5, W8

  (203) 0x41fd98 LDR	W12, [SP, #108]

  (203) 0x41fd9c LDP	X13, X28, [X23]

  (203) 0x41fda0 LDP	X27, X26, [X23, #16]

  (203) 0x41fda4 STR	X13, [SP, #120]

  (203) 0x41fda8 MSUB	W10, W9, W8, W5

  (203) 0x41fdac ADD	W11, W9, W24

  (203) 0x41fdb0 LDP	X25, X24, [X23, #32]

  (203) 0x41fdb4 SBFM	X19, X11, #0, #31

  (203) 0x41fdb8 ADD	W18, W10, W12

  (203) 0x41fdbc LDR	X23, [X23, #48]

  (203) 0x41fdc0 SUB	W21, W21, W18

  (203) 0x41fdc4 CMP	W3, W21

  (203) 0x41fdc8 CSEL	W14, W3, W21, #9

  (203) 0x41fdcc ADD	W30, W5, W14

  (203) 0x41fdd0 CMP	W5, W30

  (203) 0x41fdd4 B.CS	41ffc8

      (204) 0x41fdd8 SBFM	X0, X18, #0, #31

      (204) 0x41fddc LDR	X6, [X26]

      (204) 0x41fde0 SUB	W15, W14, #1

      (204) 0x41fde4 ADD	X5, X0, #1

      (204) 0x41fde8 LDR	X18, [X23]

      (204) 0x41fdec ADD	X12, X5, X15

      (204) 0x41fdf0 LDR	X2, [X25]

      (204) 0x41fdf4 MADD	X8, X19, X6, XZR

      (204) 0x41fdf8 LDR	X16, [X23, #16]

      (204) 0x41fdfc MADD	X17, X19, X18, XZR

      (204) 0x41fe00 LDR	X4, [X25, #16]

      (204) 0x41fe04 MADD	X3, X19, X2, XZR

      (204) 0x41fe08 LDR	X7, [X26, #16]

      (204) 0x41fe0c ADD	X18, X16, X17,LSL #3

      (204) 0x41fe10 LDR	X11, [SP, #120]

      (204) 0x41fe14 ADD	X17, X4, X3,LSL #3

      (204) 0x41fe18 LDR	X1, [X24]

      (204) 0x41fe1c ADD	X16, X7, X8,LSL #3

      (204) 0x41fe20 LDR	X9, [X27]

      (204) 0x41fe24 LDR	X10, [X28]

      (204) 0x41fe28 MADD	X21, X19, X1, XZR

      (204) 0x41fe2c LDR	X14, [X11, #8]

      (204) 0x41fe30 MADD	X6, X19, X9, XZR

      (204) 0x41fe34 LDR	X13, [X24, #16]

      (204) 0x41fe38 MADD	X7, X19, X10, XZR

      (204) 0x41fe3c LDR	X8, [X27, #16]

      (204) 0x41fe40 LDR	X4, [X28, #16]

      (204) 0x41fe44 SUB	W15, W0, #2

      (204) 0x41fe48 SUB	X2, X0, #1

      (204) 0x41fe4c LDR	D6, [X17, X0,LSL #3]

      (204) 0x41fe50 ORR	X3, XZR, X0

      (204) 0x41fe54 SBFM	X1, X15, #0, #31

      (204) 0x41fe58 ADD	W9, W0, #1

      (204) 0x41fe5c ORR	X11, XZR, X2

      (204) 0x41fe60 FCMPE	D6, #0

      (204) 0x41fe64 B.GT	41fe80

    (205) 0x41fe68 CMP	W20, W9

    (205) 0x41fe6c CSEL	W1, W20, W9, #13

    (205) 0x41fe70 SBFM	X11, X1, #0, #31

    (205) 0x41fe74 ORR	X3, XZR, X2

    (205) 0x41fe78 ORR	X1, XZR, X11

    (205) 0x41fe7c ORR	X2, XZR, X0

    (205) 0x41fe80 ADD	X9, X21, X2

    (205) 0x41fe84 FABS	D3, D6

    (205) 0x41fe88 ADD	X10, X7, X2

    (205) 0x41fe8c ADD	X15, X7, X3

    (205) 0x41fe90 LDR	D1, [X14, X11,LSL #3]

    (205) 0x41fe94 ADD	X11, X6, X1

    (205) 0x41fe98 ADD	X1, X7, X1

    (205) 0x41fe9c ADD	X2, X6, X2

    (205) 0x41fea0 LDR	D2, [X13, X9,LSL #3]

    (205) 0x41fea4 ADD	X3, X6, X3

    (205) 0x41fea8 LDR	D5, [X14, X0,LSL #3]

    (205) 0x41feac LDR	D0, [X4, X10,LSL #3]

    (205) 0x41feb0 FDIV	D20, D3, D2

    (205) 0x41feb4 LDR	D19, [X4, X15,LSL #3]

    (205) 0x41feb8 LDR	D4, [X4, X1,LSL #3]

    (205) 0x41febc FDIV	D23, D5, D1

    (205) 0x41fec0 FSUB	D21, D19, S0

    (205) 0x41fec4 FSUB	D24, D0, S4

    (205) 0x41fec8 FCMPE	D21, #0

    (205) 0x41fecc FABS	D25, D21

    (205) 0x41fed0 FMUL	D27, D21, D24

    (205) 0x41fed4 FABS	D26, D24

    (205) 0x41fed8 FMINNM	D22, D25, D26

    (205) 0x41fedc FADD	D29, D20, D7

    (205) 0x41fee0 FSUB	D28, D7, S20

    (205) 0x41fee4 FSUB	D30, D18, S20

    (205) 0x41fee8 FCSEL	D31, D16, D7, #9

    (205) 0x41feec FCMPE	D27, #0

    (205) 0x41fef0 FMUL	D5, D23, D29

    (205) 0x41fef4 B.LS	41ff10

    (205) 0x41fef8 FMUL	D3, D25, D30

    (205) 0x41fefc FMADD	D1, D26, D5, D3

    (205) 0x41ff00 FMUL	D2, D1, D17

    (205) 0x41ff04 FMINNM	D20, D2, D22

    (205) 0x41ff08 FMUL	D19, D20, D28

    (205) 0x41ff0c FMADD	D0, D19, D31, D0

    (205) 0x41ff10 FMUL	D24, D0, D6

    (205) 0x41ff14 STR	D24, [X16, X0,LSL #3]

    (205) 0x41ff18 FABS	D6, D24

    (205) 0x41ff1c LDR	D4, [X8, X2,LSL #3]

    (205) 0x41ff20 LDR	D21, [X8, X3,LSL #3]

    (205) 0x41ff24 LDR	D25, [X8, X11,LSL #3]

    (205) 0x41ff28 LDR	D26, [X4, X10,LSL #3]

    (205) 0x41ff2c FMUL	D23, D4, D24

    (205) 0x41ff30 FSUB	D27, D21, S4

    (205) 0x41ff34 LDR	D22, [X13, X9,LSL #3]

    (205) 0x41ff38 FSUB	D28, D4, S25

    (205) 0x41ff3c FABS	D31, D27

    (205) 0x41ff40 FCMPE	D27, #0

    (205) 0x41ff44 FMUL	D29, D22, D26

    (205) 0x41ff48 FMUL	D2, D27, D28

    (205) 0x41ff4c FABS	D20, D28

    (205) 0x41ff50 FMINNM	D19, D31, D20

    (205) 0x41ff54 FMUL	D30, D31, D30

    (205) 0x41ff58 FCSEL	D3, D16, D7, #9

    (205) 0x41ff5c FCMPE	D2, #0

    (205) 0x41ff60 FMADD	D5, D20, D5, D30

    (205) 0x41ff64 B.LS	41ffb4

    (205) 0x41ff68 FDIV	D0, D6, D29

    (205) 0x41ff6c FMUL	D1, D5, D17

    (205) 0x41ff70 FMINNM	D21, D1, D19

    (205) 0x41ff74 FSUB	D6, D7, S0

    (205) 0x41ff78 FMUL	D25, D6, D21

    (205) 0x41ff7c FMADD	D4, D25, D3, D4

    (205) 0x41ff80 FMUL	D24, D4, D24

    (205) 0x41ff84 STR	D24, [X18, X0,LSL #3]

    (205) 0x41ff88 ORR	X0, XZR, X5

    (205) 0x41ff8c CMP	X5, X12

    (205) 0x41ff90 B.EQ	41ffc4

    (205) 0x41ff94 ADD	X5, X5, #1

    (205) 0x41ff98 B	41fe44

(202) 0x41ff9c LDP	X25, X26, [SP, #64]

(202) 0x41ffa0 LDP	X19, X20, [SP, #16]

(202) 0x41ffa4 LDP	X21, X22, [SP, #32]

(202) 0x41ffa8 LDP	X23, X24, [SP, #48]

(202) 0x41ffac LDP	X29, X30, [SP], #128

(202) 0x41ffb0 RET

  (201) 0x41ffb4 STR	D23, [X18, X0,LSL #3]

  (201) 0x41ffb8 ORR	X0, XZR, X5

  (201) 0x41ffbc CMP	X5, X12

  (201) 0x41ffc0 B.NE	41ff94

(202) 0x41ffc4 ORR	W5, WZR, W30

  (203) 0x41ffc8 ADD	X19, X19, #1

  (203) 0x41ffcc ADD	W30, W19, #0

  (203) 0x41ffd0 CMP	W22, W30

  (203) 0x41ffd4 B.LE	41ffe8

  (203) 0x41ffd8 LDP	W21, W12, [SP, #112]

  (203) 0x41ffdc LDR	W18, [SP, #108]

  (203) 0x41ffe0 SUB	W3, W12, W5

  (203) 0x41ffe4 B	41fdc4

  (203) 0x41ffe8 LDP	X19, X20, [SP, #16]

  (203) 0x41ffec LDP	X21, X22, [SP, #32]

  (203) 0x41fff0 LDP	X23, X24, [SP, #48]

  (203) 0x41fff4 LDP	X25, X26, [SP, #64]

  (203) 0x41fff8 LDP	X27, X28, [SP, #80]

  (203) 0x41fffc LDP	X29, X30, [SP], #128

  (203) 0x420000 RET

  (203) 0x420004 ADD	W3, W3, #1

  (203) 0x420008 MOVZ	W5, #0

  (203) 0x42000c B	41fd5c

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:65-71,77-110

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.62 cycles (7.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.88
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP W24, W22, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W0, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W24, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W22, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X23, #60]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41ffa0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W25, W22, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W1, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41ff9c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W2, W21, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W25, W2, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR W2, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W3, W26, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W4, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W5, W3, W19, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 420004 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:65-71,77-110

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.88
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP W24, W22, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W0, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W24, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W22, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X23, #60]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41ffa0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W25, W22, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W1, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41ff9c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W2, W21, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W25, W2, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR W2, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W3, W26, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W4, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W5, W3, W19, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 420004 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.86	1.57
▼Loop 202 - advec_cell.cpp:65-110 - exec–	0	0
▼Loop 201 - advec_cell.cpp:71-110 - exec–	1.59	0.36
▼Loop 205 - advec_cell.cpp:71-110 - exec–	4.77	1.09
○Loop 204 - advec_cell.cpp:71-110 - exec	0.5	0.12
○Loop 203 - advec_cell.cpp:65-110 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code