OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage: 2.74%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 208 - 216

--------------------------------------------------------------------------------

208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

0x41faa8 STP	X29, X30, [SP, #944]!

0x41faac ADD	X29, SP, #0

0x41fab0 STP	X19, X20, [SP, #16]

0x41fab4 STP	X25, X26, [SP, #64]

0x41fab8 LDP	W25, W19, [X0, #56]

0x41fabc STP	X23, X24, [SP, #48]

0x41fac0 ORR	X23, XZR, X0

0x41fac4 LDR	W20, [X0, #48]

0x41fac8 ADD	W25, W25, #1

0x41facc ADD	W19, W19, #2

0x41fad0 LDR	W0, [X0, #52]

0x41fad4 CMP	W25, W19

0x41fad8 B.GE	41fcb4

0x41fadc ADD	W20, W20, #1

0x41fae0 STP	X21, X22, [SP, #32]

0x41fae4 ADD	W22, W0, #2

0x41fae8 SUB	W26, W19, W25

0x41faec CMP	W20, W22

0x41faf0 B.GE	41fcb0

0x41faf4 SUB	W21, W22, W20

0x41faf8 BL	403530

0x41fafc MADD	W26, W26, W21, WZR

0x41fb00 ORR	W24, WZR, W0

0x41fb04 BL	4033c0

0x41fb08 ORR	W1, WZR, W0

0x41fb0c UDIV	W3, W26, W24

0x41fb10 MSUB	W2, W3, W24, W26

0x41fb14 CMP	W0, W2

0x41fb18 B.CC	41fcc8

(197) 0x41fb1c MADD	W7, W3, W1, W2

(197) 0x41fb20 ADD	W17, W3, W7

(197) 0x41fb24 CMP	W7, W17

(197) 0x41fb28 B.CS	41fcb0

(197) 0x41fb2c UDIV	W4, W7, W21

(197) 0x41fb30 MOVZ	W18, #0

(197) 0x41fb34 CNTD	X10, ALL

(197) 0x41fb38 PTRUE	P1.B, ALL

(197) 0x41fb3c LDP	X16, X15, [X23]

(197) 0x41fb40 LDP	X14, X13, [X23, #16]

(197) 0x41fb44 LDP	X12, X11, [X23, #32]

(197) 0x41fb48 MSUB	W5, W4, W21, W7

(197) 0x41fb4c ADD	W6, W4, W25

(197) 0x41fb50 SBFM	X9, X6, #0, #31

(197) 0x41fb54 ADD	W8, W5, W20

(197) 0x41fb58 SUB	W30, W22, W8

(197) 0x41fb5c CMP	W3, W30

(197) 0x41fb60 CSEL	X3, X3, X30, #9

(197) 0x41fb64 ADD	W30, W7, W3

(197) 0x41fb68 CMP	W7, W30

(197) 0x41fb6c B.CS	41fc9c

  (199) 0x41fb70 LDR	X7, [X11]

  (199) 0x41fb74 SBFM	X5, X8, #0, #31

  (199) 0x41fb78 MOVZ	X0, #0

  (199) 0x41fb7c WHILELO	P0.D, XZR, X3

  (199) 0x41fb80 LDR	X8, [X11, #16]

  (199) 0x41fb84 LDR	X1, [X13]

  (199) 0x41fb88 MADD	X23, X9, X7, XZR

  (199) 0x41fb8c LDR	X24, [X12]

  (199) 0x41fb90 ADD	X25, X7, X23

  (199) 0x41fb94 ADD	X22, X23, X5

  (199) 0x41fb98 ADD	X26, X25, X5

  (199) 0x41fb9c ADD	X23, X8, X22,LSL #3

  (199) 0x41fba0 ADD	X7, X8, X26,LSL #3

  (199) 0x41fba4 LDR	X8, [X14]

  (199) 0x41fba8 MADD	X2, X9, X1, XZR

  (199) 0x41fbac MADD	X6, X9, X24, X5

  (199) 0x41fbb0 LDR	X26, [X14, #16]

  (199) 0x41fbb4 ADD	X4, X1, X2

  (199) 0x41fbb8 ADD	X25, X2, X5

  (199) 0x41fbbc MADD	X24, X9, X8, XZR

  (199) 0x41fbc0 ADD	X22, X4, X5

  (199) 0x41fbc4 ADD	X1, X8, X24

  (199) 0x41fbc8 ADD	X2, X24, X5

  (199) 0x41fbcc LDR	X24, [X15]

  (199) 0x41fbd0 ADD	X4, X1, X5

  (199) 0x41fbd4 ADD	X8, X26, X4,LSL #3

  (199) 0x41fbd8 ADD	X26, X26, X2,LSL #3

  (199) 0x41fbdc LDR	X2, [X16]

  (199) 0x41fbe0 MADD	X1, X9, X24, X5

  (199) 0x41fbe4 MADD	X24, X9, X2, X5

  (199) 0x41fbe8 LDR	X5, [X13, #16]

  (199) 0x41fbec ADD	X4, X5, X22,LSL #3

  (199) 0x41fbf0 LDR	X22, [X16, #16]

  (199) 0x41fbf4 ADD	X25, X5, X25,LSL #3

  (199) 0x41fbf8 LDR	X5, [X15, #16]

  (199) 0x41fbfc ADD	X2, X22, X24,LSL #3

  (199) 0x41fc00 LDR	X24, [X12, #16]

  (199) 0x41fc04 ADD	X1, X5, X1,LSL #3

  (199) 0x41fc08 ADD	X6, X24, X6,LSL #3

    (198) 0x41fc0c LD1D	{Z2.D}, P0/Z, [X6, X0,LSL #3]

    (198) 0x41fc10 LD1D	{Z0.D}, P0/Z, [X2, X0,LSL #3]

    (198) 0x41fc14 LD1D	{Z1.D}, P0/Z, [X25, X0,LSL #3]

    (198) 0x41fc18 LD1D	{Z6.D}, P0/Z, [X4, X0,LSL #3]

    (198) 0x41fc1c LD1D	{Z3.D}, P0/Z, [X23, X0,LSL #3]

    (198) 0x41fc20 LD1D	{Z16.D}, P0/Z, [X7, X0,LSL #3]

    (198) 0x41fc24 LD1D	{Z17.D}, P0/Z, [X1, X0,LSL #3]

    (198) 0x41fc28 LD1D	{Z19.D}, P0/Z, [X8, X0,LSL #3]

    (198) 0x41fc2c LD1D	{Z21.D}, P0/Z, [X26, X0,LSL #3]

    (198) 0x41fc30 FMUL	Z5.D, Z2.D, Z0.D

    (198) 0x41fc34 FADD	Z4.D, Z1.D, Z2.D

    (198) 0x41fc38 FSUB	Z18.D, Z3.D, Z16.D

    (198) 0x41fc3c FSUB	Z7.D, Z4.D, Z6.D

    (198) 0x41fc40 FMAD	Z17.D, P1/M, Z5.D, Z18.D

    (198) 0x41fc44 FSUB	Z20.D, Z5.D, Z19.D

    (198) 0x41fc48 FADD	Z22.D, Z20.D, Z21.D

    (198) 0x41fc4c FDIVR	Z7.D, P1/M, Z7.D, Z22.D

    (198) 0x41fc50 FDIVR	Z22.D, P1/M, Z22.D, Z17.D

    (198) 0x41fc54 ST1D	{Z7.D}, P0, [X2, X0,LSL #3]

    (198) 0x41fc58 ST1D	{Z22.D}, P0, [X1, X0,LSL #3]

    (198) 0x41fc5c ADD	X0, X0, X10

    (198) 0x41fc60 WHILELO	P0.D, X0, X3

    (198) 0x41fc64 B.NE	41fc0c

  (199) 0x41fc68 ADD	X9, X9, #1

  (199) 0x41fc6c ADD	W3, W18, W9

  (199) 0x41fc70 CMP	W19, W3

  (199) 0x41fc74 B.LE	41fcb0

  (199) 0x41fc78 SUB	W3, W17, W30

  (199) 0x41fc7c ORR	W7, WZR, W30

  (199) 0x41fc80 ORR	W30, WZR, W21

  (199) 0x41fc84 ORR	W8, WZR, W20

  (199) 0x41fc88 CMP	W3, W30

  (199) 0x41fc8c CSEL	X3, X3, X30, #9

  (199) 0x41fc90 ADD	W30, W7, W3

  (199) 0x41fc94 CMP	W7, W30

  (199) 0x41fc98 B.CC	41fb70

  (200) 0x41fc9c ADD	X9, X9, #1

  (200) 0x41fca0 ORR	W30, WZR, W7

  (200) 0x41fca4 ADD	W3, W18, W9

  (200) 0x41fca8 CMP	W19, W3

  (200) 0x41fcac B.GT	41fc78

(197) 0x41fcb0 LDP	X21, X22, [SP, #32]

(197) 0x41fcb4 LDP	X19, X20, [SP, #16]

(197) 0x41fcb8 LDP	X23, X24, [SP, #48]

(197) 0x41fcbc LDP	X25, X26, [SP, #64]

(197) 0x41fcc0 LDP	X29, X30, [SP], #80

(197) 0x41fcc4 RET

(197) 0x41fcc8 ADD	W3, W3, #1

(197) 0x41fccc MOVZ	W2, #0

(197) 0x41fcd0 B	41fb1c

0x41fcd4 HINT	#0

0x41fcd8 HINT	#0

0x41fcdc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:208-216

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41faa8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41fcb4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41fcb0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W2, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41fcc8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:208-216

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41faa8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41fcb4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41fcb0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W2, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41fcc8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	2.74	0.63
▼Loop 197 - advec_cell.cpp:208-216 - exec–	0	0
▼Loop 199 - advec_cell.cpp:210-216 - exec–	0.02	0
○Loop 198 - advec_cell.cpp:211-216 - exec	2.72	0.62
○Loop 200 - advec_cell.cpp:210-214 - exec	0	0

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ASM code

Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code