OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:146-150 [...]	Coverage: 0.54%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 146 - 150

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

148:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

149:           pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

150:           post_vol(i, j) = volume(i, j);

0x41f8ec STP	X29, X30, [SP, #944]!

0x41f8f0 ADD	X29, SP, #0

0x41f8f4 STP	X19, X20, [SP, #16]

0x41f8f8 STP	X25, X26, [SP, #64]

0x41f8fc LDP	W25, W19, [X0, #40]

0x41f900 STP	X23, X24, [SP, #48]

0x41f904 ORR	X23, XZR, X0

0x41f908 LDR	W20, [X0, #32]

0x41f90c SUB	W25, W25, #1

0x41f910 ADD	W19, W19, #4

0x41f914 LDR	W0, [X0, #36]

0x41f918 CMP	W25, W19

0x41f91c B.GE	41fa88

0x41f920 SUB	W20, W20, #1

0x41f924 STP	X21, X22, [SP, #32]

0x41f928 ADD	W22, W0, #4

0x41f92c SUB	W26, W19, W25

0x41f930 CMP	W20, W22

0x41f934 B.GE	41fa84

0x41f938 SUB	W21, W22, W20

0x41f93c BL	403530

0x41f940 MADD	W26, W26, W21, WZR

0x41f944 ORR	W24, WZR, W0

0x41f948 BL	4033c0

0x41f94c ORR	W2, WZR, W0

0x41f950 UDIV	W1, W26, W24

0x41f954 MSUB	W3, W1, W24, W26

0x41f958 CMP	W0, W3

0x41f95c B.CC	41fa9c

(193) 0x41f960 MADD	W16, W1, W2, W3

(193) 0x41f964 ADD	W13, W1, W16

(193) 0x41f968 CMP	W16, W13

(193) 0x41f96c B.CS	41fa84

(193) 0x41f970 UDIV	W4, W16, W21

(193) 0x41f974 MOVZ	W14, #0

(193) 0x41f978 CNTD	X8, ALL

(193) 0x41f97c LDP	X12, X11, [X23]

(193) 0x41f980 LDP	X10, X9, [X23, #16]

(193) 0x41f984 MSUB	W7, W4, W21, W16

(193) 0x41f988 ADD	W5, W4, W25

(193) 0x41f98c SBFM	X17, X5, #0, #31

(193) 0x41f990 ADD	W2, W7, W20

(193) 0x41f994 SUB	W15, W22, W2

(193) 0x41f998 CMP	W1, W15

(193) 0x41f99c CSEL	X30, X1, X15, #9

(193) 0x41f9a0 ADD	W15, W16, W30

(193) 0x41f9a4 CMP	W16, W15

(193) 0x41f9a8 B.CS	41fa6c

  (195) 0x41f9ac LDR	X22, [X11]

  (195) 0x41f9b0 SBFM	X23, X2, #0, #31

  (195) 0x41f9b4 ADD	X16, X17, #1

  (195) 0x41f9b8 MOVZ	X0, #0

  (195) 0x41f9bc WHILELO	P0.D, XZR, X30

  (195) 0x41f9c0 LDR	X6, [X9]

  (195) 0x41f9c4 LDR	X18, [X10]

  (195) 0x41f9c8 MADD	X2, X17, X22, X22

  (195) 0x41f9cc LDR	X24, [X11, #16]

  (195) 0x41f9d0 MADD	X25, X17, X6, X23

  (195) 0x41f9d4 LDR	X7, [X12]

  (195) 0x41f9d8 SUB	X1, X2, X22

  (195) 0x41f9dc ADD	X3, X2, X23

  (195) 0x41f9e0 ADD	X4, X1, X23

  (195) 0x41f9e4 MADD	X26, X17, X18, X23

  (195) 0x41f9e8 LDR	X22, [X9, #16]

  (195) 0x41f9ec ADD	X5, X24, X4,LSL #3

  (195) 0x41f9f0 ADD	X6, X24, X3,LSL #3

  (195) 0x41f9f4 LDR	X18, [X12, #16]

  (195) 0x41f9f8 MADD	X17, X17, X7, X23

  (195) 0x41f9fc LDR	X24, [X10, #16]

  (195) 0x41fa00 ADD	X25, X22, X25,LSL #3

  (195) 0x41fa04 ADD	X23, X18, X17,LSL #3

  (195) 0x41fa08 ADD	X26, X24, X26,LSL #3

    (194) 0x41fa0c LD1D	{Z2.D}, P0/Z, [X23, X0,LSL #3]

    (194) 0x41fa10 LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

    (194) 0x41fa14 LD1D	{Z1.D}, P0/Z, [X5, X0,LSL #3]

    (194) 0x41fa18 FADD	Z3.D, Z0.D, Z2.D

    (194) 0x41fa1c FSUB	Z4.D, Z3.D, Z1.D

    (194) 0x41fa20 ST1D	{Z4.D}, P0, [X26, X0,LSL #3]

    (194) 0x41fa24 LD1D	{Z5.D}, P0/Z, [X23, X0,LSL #3]

    (194) 0x41fa28 ST1D	{Z5.D}, P0, [X25, X0,LSL #3]

    (194) 0x41fa2c ADD	X0, X0, X8

    (194) 0x41fa30 WHILELO	P0.D, X0, X30

    (194) 0x41fa34 B.NE	41fa0c

  (195) 0x41fa38 ADD	W30, W14, W16

  (195) 0x41fa3c ORR	X17, XZR, X16

  (195) 0x41fa40 CMP	W19, W30

  (195) 0x41fa44 B.LE	41fa84

  (195) 0x41fa48 SUB	W1, W13, W15

  (195) 0x41fa4c ORR	W16, WZR, W15

  (195) 0x41fa50 ORR	W15, WZR, W21

  (195) 0x41fa54 ORR	W2, WZR, W20

  (195) 0x41fa58 CMP	W1, W15

  (195) 0x41fa5c CSEL	X30, X1, X15, #9

  (195) 0x41fa60 ADD	W15, W16, W30

  (195) 0x41fa64 CMP	W16, W15

  (195) 0x41fa68 B.CC	41f9ac

  (196) 0x41fa6c ORR	W15, WZR, W16

  (196) 0x41fa70 ADD	X16, X17, #1

  (196) 0x41fa74 ADD	W30, W14, W16

  (196) 0x41fa78 ORR	X17, XZR, X16

  (196) 0x41fa7c CMP	W19, W30

  (196) 0x41fa80 B.GT	41fa48

(193) 0x41fa84 LDP	X21, X22, [SP, #32]

(193) 0x41fa88 LDP	X19, X20, [SP, #16]

(193) 0x41fa8c LDP	X23, X24, [SP, #48]

(193) 0x41fa90 LDP	X25, X26, [SP, #64]

(193) 0x41fa94 LDP	X29, X30, [SP], #80

(193) 0x41fa98 RET

(193) 0x41fa9c ADD	W1, W1, #1

(193) 0x41faa0 MOVZ	W3, #0

(193) 0x41faa4 B	41f960

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:146-150

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f8ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41fa88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41fa84 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41fa9c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:146-150

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f8ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41fa88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41fa84 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41fa9c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.54	0.13
▼Loop 193 - advec_cell.cpp:146-150 - exec–	0	0
▼Loop 195 - advec_cell.cpp:148-150 - exec–	0	0
○Loop 194 - advec_cell.cpp:149-150 - exec	0.54	0.13
○Loop 196 - advec_cell.cpp:150-150 - exec	0	0

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Vectorization

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code