OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage: 0.67%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

0x41f6e8 STP	X29, X30, [SP, #944]!

0x41f6ec ADD	X29, SP, #0

0x41f6f0 STP	X19, X20, [SP, #16]

0x41f6f4 STP	X25, X26, [SP, #64]

0x41f6f8 LDP	W25, W19, [X0, #48]

0x41f6fc LDP	W20, W3, [X0, #40]

0x41f700 SUB	W25, W25, #1

0x41f704 ADD	W19, W19, #4

0x41f708 CMP	W25, W19

0x41f70c B.GE	41f8c8

0x41f710 SUB	W20, W20, #1

0x41f714 STP	X21, X22, [SP, #32]

0x41f718 ADD	W22, W3, #4

0x41f71c SUB	W26, W19, W25

0x41f720 CMP	W20, W22

0x41f724 B.GE	41f8e4

0x41f728 SUB	W21, W22, W20

0x41f72c STP	X23, X24, [SP, #48]

0x41f730 ORR	X23, XZR, X0

0x41f734 MADD	W26, W26, W21, WZR

0x41f738 BL	403530

0x41f73c ORR	W24, WZR, W0

0x41f740 BL	4033c0

0x41f744 UDIV	W1, W26, W24

0x41f748 ORR	W2, WZR, W0

0x41f74c MSUB	W0, W1, W24, W26

0x41f750 CMP	W2, W0

0x41f754 B.CC	41f8d8

(189) 0x41f758 MADD	W18, W1, W2, W0

(189) 0x41f75c ADD	W15, W1, W18

(189) 0x41f760 CMP	W18, W15

(189) 0x41f764 B.CS	41f8c0

(189) 0x41f768 UDIV	W4, W18, W21

(189) 0x41f76c MOVZ	W16, #0

(189) 0x41f770 CNTD	X9, ALL

(189) 0x41f774 LDP	X14, X13, [X23]

(189) 0x41f778 LDP	X12, X11, [X23, #16]

(189) 0x41f77c LDR	X10, [X23, #32]

(189) 0x41f780 MSUB	W5, W4, W21, W18

(189) 0x41f784 ADD	W6, W4, W25

(189) 0x41f788 SBFM	X30, X6, #0, #31

(189) 0x41f78c ADD	W3, W5, W20

(189) 0x41f790 SUB	W17, W22, W3

(189) 0x41f794 CMP	W1, W17

(189) 0x41f798 CSEL	X25, X1, X17, #9

(189) 0x41f79c ADD	W17, W18, W25

(189) 0x41f7a0 CMP	W18, W17

(189) 0x41f7a4 B.CS	41f8a4

  (191) 0x41f7a8 LDR	X24, [X12]

  (191) 0x41f7ac SBFM	X22, X3, #0, #31

  (191) 0x41f7b0 ADD	X18, X30, #1

  (191) 0x41f7b4 ADD	X8, X22, #1

  (191) 0x41f7b8 MOVZ	X0, #0

  (191) 0x41f7bc WHILELO	P0.D, XZR, X25

  (191) 0x41f7c0 LDR	X7, [X10]

  (191) 0x41f7c4 LDR	X3, [X11]

  (191) 0x41f7c8 MADD	X1, X30, X24, X24

  (191) 0x41f7cc LDR	X6, [X12, #16]

  (191) 0x41f7d0 MADD	X23, X30, X7, X22

  (191) 0x41f7d4 SUB	X2, X1, X24

  (191) 0x41f7d8 LDR	X7, [X10, #16]

  (191) 0x41f7dc ADD	X4, X1, X22

  (191) 0x41f7e0 ADD	X5, X2, X22

  (191) 0x41f7e4 MADD	X26, X30, X3, X22

  (191) 0x41f7e8 LDR	X2, [X13]

  (191) 0x41f7ec ADD	X1, X6, X5,LSL #3

  (191) 0x41f7f0 ADD	X3, X6, X4,LSL #3

  (191) 0x41f7f4 LDR	X6, [X14]

  (191) 0x41f7f8 ADD	X24, X7, X23,LSL #3

  (191) 0x41f7fc LDR	X23, [X13, #16]

  (191) 0x41f800 MADD	X4, X30, X2, XZR

  (191) 0x41f804 ADD	X5, X4, X22

  (191) 0x41f808 ADD	X8, X8, X4

  (191) 0x41f80c ADD	X2, X23, X8,LSL #3

  (191) 0x41f810 ADD	X7, X23, X5,LSL #3

  (191) 0x41f814 MADD	X23, X30, X6, X22

  (191) 0x41f818 LDR	X30, [X11, #16]

  (191) 0x41f81c ADD	X22, X30, X26,LSL #3

  (191) 0x41f820 LDR	X26, [X14, #16]

  (191) 0x41f824 ADD	X4, X26, X23,LSL #3

    (190) 0x41f828 LD1D	{Z1.D}, P0/Z, [X4, X0,LSL #3]

    (190) 0x41f82c LD1D	{Z0.D}, P0/Z, [X3, X0,LSL #3]

    (190) 0x41f830 LD1D	{Z3.D}, P0/Z, [X1, X0,LSL #3]

    (190) 0x41f834 LD1D	{Z5.D}, P0/Z, [X7, X0,LSL #3]

    (190) 0x41f838 LD1D	{Z2.D}, P0/Z, [X2, X0,LSL #3]

    (190) 0x41f83c FADD	Z4.D, Z0.D, Z1.D

    (190) 0x41f840 FADD	Z6.D, Z5.D, Z3.D

    (190) 0x41f844 FSUB	Z7.D, Z4.D, Z6.D

    (190) 0x41f848 FADD	Z16.D, Z7.D, Z2.D

    (190) 0x41f84c ST1D	{Z16.D}, P0, [X22, X0,LSL #3]

    (190) 0x41f850 LD1D	{Z17.D}, P0/Z, [X1, X0,LSL #3]

    (190) 0x41f854 LD1D	{Z18.D}, P0/Z, [X3, X0,LSL #3]

    (190) 0x41f858 FSUB	Z19.D, Z17.D, Z18.D

    (190) 0x41f85c FADD	Z20.D, Z19.D, Z16.D

    (190) 0x41f860 ST1D	{Z20.D}, P0, [X24, X0,LSL #3]

    (190) 0x41f864 ADD	X0, X0, X9

    (190) 0x41f868 WHILELO	P0.D, X0, X25

    (190) 0x41f86c B.NE	41f828

  (191) 0x41f870 ADD	W25, W16, W18

  (191) 0x41f874 ORR	X30, XZR, X18

  (191) 0x41f878 CMP	W19, W25

  (191) 0x41f87c B.LE	41f8c0

  (191) 0x41f880 SUB	W1, W15, W17

  (191) 0x41f884 ORR	W18, WZR, W17

  (191) 0x41f888 ORR	W17, WZR, W21

  (191) 0x41f88c ORR	W3, WZR, W20

  (191) 0x41f890 CMP	W1, W17

  (191) 0x41f894 CSEL	X25, X1, X17, #9

  (191) 0x41f898 ADD	W17, W18, W25

  (191) 0x41f89c CMP	W18, W17

  (191) 0x41f8a0 B.CC	41f7a8

  (192) 0x41f8a4 ORR	W17, WZR, W18

  (192) 0x41f8a8 ADD	X18, X30, #1

  (192) 0x41f8ac ADD	W25, W16, W18

  (192) 0x41f8b0 ORR	X30, XZR, X18

  (192) 0x41f8b4 CMP	W19, W25

  (192) 0x41f8b8 B.GT	41f880

(189) 0x41f8bc HINT	#0

(189) 0x41f8c0 LDP	X21, X22, [SP, #32]

(189) 0x41f8c4 LDP	X23, X24, [SP, #48]

(189) 0x41f8c8 LDP	X19, X20, [SP, #16]

(189) 0x41f8cc LDP	X25, X26, [SP, #64]

(189) 0x41f8d0 LDP	X29, X30, [SP], #80

(189) 0x41f8d4 RET

(189) 0x41f8d8 ADD	W1, W1, #1

(189) 0x41f8dc MOVZ	W0, #0

(189) 0x41f8e0 B	41f758

0x41f8e4 LDP	X21, X22, [SP, #32]

0x41f8e8 B	41f8c8

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:136-140

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f6e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f8c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f8e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f8d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 41f8c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:136-140

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f6e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f8c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f8e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f8d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 41f8c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.67	0.15
▼Loop 189 - advec_cell.cpp:136-140 - exec–	0	0
▼Loop 191 - advec_cell.cpp:138-140 - exec–	0.02	0
○Loop 190 - advec_cell.cpp:139-140 - exec	0.65	0.15
○Loop 192 - advec_cell.cpp:140-140 - exec	0	0

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code