OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage: 2.7%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

0x41f4a4 STP	X29, X30, [SP, #928]!

0x41f4a8 ADD	X29, SP, #0

0x41f4ac STP	X19, X20, [SP, #16]

0x41f4b0 STP	X25, X26, [SP, #64]

0x41f4b4 LDP	W25, W19, [X0, #56]

0x41f4b8 STP	X23, X24, [SP, #48]

0x41f4bc ORR	X23, XZR, X0

0x41f4c0 LDR	W20, [X0, #48]

0x41f4c4 ADD	W25, W25, #1

0x41f4c8 ADD	W19, W19, #2

0x41f4cc LDR	W0, [X0, #52]

0x41f4d0 CMP	W25, W19

0x41f4d4 B.GE	41f6b0

0x41f4d8 ADD	W20, W20, #1

0x41f4dc STP	X21, X22, [SP, #32]

0x41f4e0 ADD	W22, W0, #2

0x41f4e4 SUB	W26, W19, W25

0x41f4e8 CMP	W20, W22

0x41f4ec B.GE	41f6c4

0x41f4f0 SUB	W21, W22, W20

0x41f4f4 BL	403530

0x41f4f8 MADD	W26, W26, W21, WZR

0x41f4fc ORR	W24, WZR, W0

0x41f500 BL	4033c0

0x41f504 ORR	W1, WZR, W0

0x41f508 UDIV	W3, W26, W24

0x41f50c MSUB	W2, W3, W24, W26

0x41f510 CMP	W0, W2

0x41f514 B.CC	41f6dc

  (184) 0x41f518 MADD	W26, W3, W1, W2

  (184) 0x41f51c ADD	W17, W3, W26

  (184) 0x41f520 CMP	W26, W17

  (184) 0x41f524 B.CS	41f6c4

(186) 0x41f528 UDIV	W4, W26, W21

(186) 0x41f52c LDP	X16, X15, [X23]

(186) 0x41f530 MOVZ	W18, #0

(186) 0x41f534 CNTD	X10, ALL

(186) 0x41f538 PTRUE	P1.B, ALL

(186) 0x41f53c LDP	X14, X13, [X23, #16]

(186) 0x41f540 LDP	X12, X11, [X23, #32]

(186) 0x41f544 STR	X27, [SP, #80]

(186) 0x41f548 MSUB	W6, W4, W21, W26

(186) 0x41f54c ADD	W5, W4, W25

(186) 0x41f550 SBFM	X9, X5, #0, #31

(186) 0x41f554 ADD	W7, W6, W20

(186) 0x41f558 SUB	W30, W22, W7

(186) 0x41f55c CMP	W3, W30

(186) 0x41f560 CSEL	X3, X3, X30, #9

(186) 0x41f564 ADD	W30, W26, W3

(186) 0x41f568 CMP	W26, W30

(186) 0x41f56c B.CS	41f694

  (187) 0x41f570 SBFM	X6, X7, #0, #31

  (187) 0x41f574 LDR	X7, [X11]

  (187) 0x41f578 MOVZ	X0, #0

  (187) 0x41f57c ADD	X1, X6, #1

  (187) 0x41f580 WHILELO	P0.D, XZR, X3

  (187) 0x41f584 LDR	X24, [X13]

  (187) 0x41f588 LDR	X5, [X14]

  (187) 0x41f58c MADD	X27, X9, X7, XZR

  (187) 0x41f590 LDR	X8, [X11, #16]

  (187) 0x41f594 MADD	X4, X9, X24, XZR

  (187) 0x41f598 LDR	X22, [X12]

  (187) 0x41f59c ADD	X23, X27, X1

  (187) 0x41f5a0 ADD	X25, X27, X6

  (187) 0x41f5a4 LDR	X2, [X13, #16]

  (187) 0x41f5a8 ADD	X26, X8, X25,LSL #3

  (187) 0x41f5ac LDR	X27, [X14, #16]

  (187) 0x41f5b0 ADD	X7, X8, X23,LSL #3

  (187) 0x41f5b4 MADD	X8, X9, X5, XZR

  (187) 0x41f5b8 MADD	X23, X9, X22, X6

  (187) 0x41f5bc ADD	X25, X8, X1

  (187) 0x41f5c0 ADD	X22, X8, X6

  (187) 0x41f5c4 ADD	X1, X4, X1

  (187) 0x41f5c8 ADD	X4, X4, X6

  (187) 0x41f5cc ADD	X8, X27, X22,LSL #3

  (187) 0x41f5d0 ADD	X24, X27, X25,LSL #3

  (187) 0x41f5d4 LDR	X22, [X16]

  (187) 0x41f5d8 ADD	X27, X2, X4,LSL #3

  (187) 0x41f5dc ADD	X5, X2, X1,LSL #3

  (187) 0x41f5e0 LDR	X2, [X15]

  (187) 0x41f5e4 LDR	X25, [X16, #16]

  (187) 0x41f5e8 MADD	X1, X9, X2, X6

  (187) 0x41f5ec LDR	X2, [X12, #16]

  (187) 0x41f5f0 MADD	X6, X9, X22, X6

  (187) 0x41f5f4 LDR	X22, [X15, #16]

  (187) 0x41f5f8 ADD	X4, X25, X6,LSL #3

  (187) 0x41f5fc ADD	X23, X2, X23,LSL #3

  (187) 0x41f600 ADD	X1, X22, X1,LSL #3

    (185) 0x41f604 LD1D	{Z2.D}, P0/Z, [X23, X0,LSL #3]

    (185) 0x41f608 LD1D	{Z0.D}, P0/Z, [X4, X0,LSL #3]

    (185) 0x41f60c LD1D	{Z1.D}, P0/Z, [X27, X0,LSL #3]

    (185) 0x41f610 LD1D	{Z6.D}, P0/Z, [X5, X0,LSL #3]

    (185) 0x41f614 LD1D	{Z3.D}, P0/Z, [X26, X0,LSL #3]

    (185) 0x41f618 LD1D	{Z16.D}, P0/Z, [X7, X0,LSL #3]

    (185) 0x41f61c LD1D	{Z17.D}, P0/Z, [X1, X0,LSL #3]

    (185) 0x41f620 LD1D	{Z19.D}, P0/Z, [X24, X0,LSL #3]

    (185) 0x41f624 LD1D	{Z21.D}, P0/Z, [X8, X0,LSL #3]

    (185) 0x41f628 FMUL	Z5.D, Z2.D, Z0.D

    (185) 0x41f62c FADD	Z4.D, Z1.D, Z2.D

    (185) 0x41f630 FSUB	Z18.D, Z3.D, Z16.D

    (185) 0x41f634 FSUB	Z7.D, Z4.D, Z6.D

    (185) 0x41f638 FMAD	Z17.D, P1/M, Z5.D, Z18.D

    (185) 0x41f63c FSUB	Z20.D, Z5.D, Z19.D

    (185) 0x41f640 FADD	Z22.D, Z20.D, Z21.D

    (185) 0x41f644 FDIVR	Z7.D, P1/M, Z7.D, Z22.D

    (185) 0x41f648 FDIVR	Z22.D, P1/M, Z22.D, Z17.D

    (185) 0x41f64c ST1D	{Z7.D}, P0, [X4, X0,LSL #3]

    (185) 0x41f650 ST1D	{Z22.D}, P0, [X1, X0,LSL #3]

    (185) 0x41f654 ADD	X0, X0, X10

    (185) 0x41f658 WHILELO	P0.D, X0, X3

    (185) 0x41f65c B.NE	41f604

  (187) 0x41f660 ADD	X9, X9, #1

  (187) 0x41f664 ADD	W3, W18, W9

  (187) 0x41f668 CMP	W19, W3

  (187) 0x41f66c B.LE	41f6a8

  (187) 0x41f670 SUB	W3, W17, W30

  (187) 0x41f674 ORR	W26, WZR, W30

  (187) 0x41f678 ORR	W30, WZR, W21

  (187) 0x41f67c ORR	W7, WZR, W20

  (187) 0x41f680 CMP	W3, W30

  (187) 0x41f684 CSEL	X3, X3, X30, #9

  (187) 0x41f688 ADD	W30, W26, W3

  (187) 0x41f68c CMP	W26, W30

  (187) 0x41f690 B.CC	41f570

  (188) 0x41f694 ADD	X9, X9, #1

  (188) 0x41f698 ORR	W30, WZR, W26

  (188) 0x41f69c ADD	W3, W18, W9

  (188) 0x41f6a0 CMP	W19, W3

  (188) 0x41f6a4 B.GT	41f670

(186) 0x41f6a8 LDP	X21, X22, [SP, #32]

(186) 0x41f6ac LDR	X27, [SP, #80]

(186) 0x41f6b0 LDP	X19, X20, [SP, #16]

(186) 0x41f6b4 LDP	X23, X24, [SP, #48]

(186) 0x41f6b8 LDP	X25, X26, [SP, #64]

(186) 0x41f6bc LDP	X29, X30, [SP], #96

(186) 0x41f6c0 RET

  (184) 0x41f6c4 LDP	X19, X20, [SP, #16]

  (184) 0x41f6c8 LDP	X21, X22, [SP, #32]

  (184) 0x41f6cc LDP	X23, X24, [SP, #48]

  (184) 0x41f6d0 LDP	X25, X26, [SP, #64]

  (184) 0x41f6d4 LDP	X29, X30, [SP], #96

  (184) 0x41f6d8 RET

  (184) 0x41f6dc ADD	W3, W3, #1

  (184) 0x41f6e0 MOVZ	W2, #0

  (184) 0x41f6e4 B	41f518

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:117-125

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f4a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f6b0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f6c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W2, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f6dc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:117-125

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f4a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f6b0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f6c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W2, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f6dc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	2.7	0.62
▼Loop 186 - advec_cell.cpp:117-125 - exec–	0	0
▼Loop 187 - advec_cell.cpp:119-125 - exec–	0.02	0
○Loop 185 - advec_cell.cpp:120-125 - exec	2.68	0.61
○Loop 188 - advec_cell.cpp:119-123 - exec	0	0
○Loop 184 - advec_cell.cpp:117-119 - exec	0	0

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