OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:54-58 [...]	Coverage: 0.48%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 54 - 58

--------------------------------------------------------------------------------

54: #pragma omp parallel for simd collapse(2)

55:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

56:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

57:           pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

58:           post_vol(i, j) = volume(i, j);

0x41f2ec STP	X29, X30, [SP, #944]!

0x41f2f0 ADD	X29, SP, #0

0x41f2f4 STP	X19, X20, [SP, #16]

0x41f2f8 STP	X25, X26, [SP, #64]

0x41f2fc LDP	W25, W19, [X0, #40]

0x41f300 STP	X23, X24, [SP, #48]

0x41f304 ORR	X23, XZR, X0

0x41f308 LDR	W20, [X0, #32]

0x41f30c SUB	W25, W25, #1

0x41f310 ADD	W19, W19, #4

0x41f314 LDR	W0, [X0, #36]

0x41f318 CMP	W25, W19

0x41f31c B.GE	41f484

0x41f320 SUB	W20, W20, #1

0x41f324 STP	X21, X22, [SP, #32]

0x41f328 ADD	W22, W0, #4

0x41f32c SUB	W26, W19, W25

0x41f330 CMP	W20, W22

0x41f334 B.GE	41f480

0x41f338 SUB	W21, W22, W20

0x41f33c BL	403530

0x41f340 MADD	W26, W26, W21, WZR

0x41f344 ORR	W24, WZR, W0

0x41f348 BL	4033c0

0x41f34c ORR	W2, WZR, W0

0x41f350 UDIV	W1, W26, W24

0x41f354 MSUB	W3, W1, W24, W26

0x41f358 CMP	W0, W3

0x41f35c B.CC	41f498

(180) 0x41f360 MADD	W24, W1, W2, W3

(180) 0x41f364 ADD	W14, W1, W24

(180) 0x41f368 CMP	W24, W14

(180) 0x41f36c B.CS	41f480

(180) 0x41f370 UDIV	W4, W24, W21

(180) 0x41f374 MOVZ	W15, #0

(180) 0x41f378 CNTD	X8, ALL

(180) 0x41f37c LDP	X13, X12, [X23]

(180) 0x41f380 LDP	X11, X10, [X23, #16]

(180) 0x41f384 MSUB	W16, W4, W21, W24

(180) 0x41f388 ADD	W5, W4, W25

(180) 0x41f38c SBFM	X7, X5, #0, #31

(180) 0x41f390 ADD	W2, W16, W20

(180) 0x41f394 SUB	W9, W22, W2

(180) 0x41f398 CMP	W1, W9

(180) 0x41f39c CSEL	X30, X1, X9, #9

(180) 0x41f3a0 ADD	W9, W24, W30

(180) 0x41f3a4 CMP	W24, W9

(180) 0x41f3a8 B.CS	41f468

  (182) 0x41f3ac LDR	X17, [X10]

  (182) 0x41f3b0 SBFM	X23, X2, #0, #31

  (182) 0x41f3b4 MOVZ	X0, #0

  (182) 0x41f3b8 ADD	X6, X23, #1

  (182) 0x41f3bc WHILELO	P0.D, XZR, X30

  (182) 0x41f3c0 LDR	X22, [X11]

  (182) 0x41f3c4 LDR	X2, [X12]

  (182) 0x41f3c8 MADD	X25, X7, X17, X23

  (182) 0x41f3cc LDR	X18, [X11, #16]

  (182) 0x41f3d0 MADD	X26, X7, X22, X23

  (182) 0x41f3d4 LDR	X17, [X13]

  (182) 0x41f3d8 MADD	X3, X7, X2, XZR

  (182) 0x41f3dc LDR	X1, [X12, #16]

  (182) 0x41f3e0 ADD	X24, X18, X26,LSL #3

  (182) 0x41f3e4 LDR	X22, [X13, #16]

  (182) 0x41f3e8 ADD	X16, X3, X23

  (182) 0x41f3ec ADD	X4, X6, X3

  (182) 0x41f3f0 MADD	X23, X7, X17, X23

  (182) 0x41f3f4 LDR	X26, [X10, #16]

  (182) 0x41f3f8 ADD	X6, X1, X4,LSL #3

  (182) 0x41f3fc ADD	X5, X1, X16,LSL #3

  (182) 0x41f400 ADD	X18, X22, X23,LSL #3

  (182) 0x41f404 ADD	X25, X26, X25,LSL #3

    (181) 0x41f408 LD1D	{Z2.D}, P0/Z, [X18, X0,LSL #3]

    (181) 0x41f40c LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

    (181) 0x41f410 LD1D	{Z1.D}, P0/Z, [X5, X0,LSL #3]

    (181) 0x41f414 FADD	Z3.D, Z0.D, Z2.D

    (181) 0x41f418 FSUB	Z4.D, Z3.D, Z1.D

    (181) 0x41f41c ST1D	{Z4.D}, P0, [X24, X0,LSL #3]

    (181) 0x41f420 LD1D	{Z5.D}, P0/Z, [X18, X0,LSL #3]

    (181) 0x41f424 ST1D	{Z5.D}, P0, [X25, X0,LSL #3]

    (181) 0x41f428 ADD	X0, X0, X8

    (181) 0x41f42c WHILELO	P0.D, X0, X30

    (181) 0x41f430 B.NE	41f408

  (182) 0x41f434 ADD	X7, X7, #1

  (182) 0x41f438 ADD	W30, W15, W7

  (182) 0x41f43c CMP	W19, W30

  (182) 0x41f440 B.LE	41f480

  (182) 0x41f444 SUB	W1, W14, W9

  (182) 0x41f448 ORR	W24, WZR, W9

  (182) 0x41f44c ORR	W9, WZR, W21

  (182) 0x41f450 ORR	W2, WZR, W20

  (182) 0x41f454 CMP	W1, W9

  (182) 0x41f458 CSEL	X30, X1, X9, #9

  (182) 0x41f45c ADD	W9, W24, W30

  (182) 0x41f460 CMP	W24, W9

  (182) 0x41f464 B.CC	41f3ac

  (183) 0x41f468 ADD	X7, X7, #1

  (183) 0x41f46c ORR	W9, WZR, W24

  (183) 0x41f470 ADD	W30, W15, W7

  (183) 0x41f474 CMP	W19, W30

  (183) 0x41f478 B.GT	41f444

(180) 0x41f47c HINT	#0

(180) 0x41f480 LDP	X21, X22, [SP, #32]

(180) 0x41f484 LDP	X19, X20, [SP, #16]

(180) 0x41f488 LDP	X23, X24, [SP, #48]

(180) 0x41f48c LDP	X25, X26, [SP, #64]

(180) 0x41f490 LDP	X29, X30, [SP], #80

(180) 0x41f494 RET

(180) 0x41f498 ADD	W1, W1, #1

(180) 0x41f49c MOVZ	W3, #0

(180) 0x41f4a0 B	41f360

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:54-58

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f2ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f484 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f480 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f498 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:54-58

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f2ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W0, [X0, #36]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f484 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f480 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W3, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f498 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.48	0.11
▼Loop 180 - advec_cell.cpp:54-58 - exec–	0.02	0
▼Loop 182 - advec_cell.cpp:56-58 - exec–	0	0
○Loop 181 - advec_cell.cpp:57-58 - exec	0.46	0.1
○Loop 183 - advec_cell.cpp:56-58 - exec	0	0

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code