OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:44-48 [...]	Coverage: 0.76%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

0x41f0e0 STP	X29, X30, [SP, #944]!

0x41f0e4 ADD	X29, SP, #0

0x41f0e8 STP	X19, X20, [SP, #16]

0x41f0ec STP	X25, X26, [SP, #64]

0x41f0f0 LDP	W25, W19, [X0, #48]

0x41f0f4 LDP	W20, W3, [X0, #40]

0x41f0f8 SUB	W25, W25, #1

0x41f0fc ADD	W19, W19, #4

0x41f100 CMP	W25, W19

0x41f104 B.GE	41f2c8

0x41f108 SUB	W20, W20, #1

0x41f10c STP	X21, X22, [SP, #32]

0x41f110 ADD	W22, W3, #4

0x41f114 SUB	W26, W19, W25

0x41f118 CMP	W20, W22

0x41f11c B.GE	41f2e4

0x41f120 SUB	W21, W22, W20

0x41f124 STP	X23, X24, [SP, #48]

0x41f128 ORR	X23, XZR, X0

0x41f12c MADD	W26, W26, W21, WZR

0x41f130 BL	403530

0x41f134 ORR	W24, WZR, W0

0x41f138 BL	4033c0

0x41f13c UDIV	W1, W26, W24

0x41f140 ORR	W2, WZR, W0

0x41f144 MSUB	W0, W1, W24, W26

0x41f148 CMP	W2, W0

0x41f14c B.CC	41f2d8

(176) 0x41f150 MADD	W18, W1, W2, W0

(176) 0x41f154 ADD	W15, W1, W18

(176) 0x41f158 CMP	W18, W15

(176) 0x41f15c B.CS	41f2c0

(176) 0x41f160 UDIV	W4, W18, W21

(176) 0x41f164 MOVZ	W16, #0

(176) 0x41f168 CNTD	X9, ALL

(176) 0x41f16c LDP	X14, X13, [X23]

(176) 0x41f170 LDP	X12, X11, [X23, #16]

(176) 0x41f174 LDR	X10, [X23, #32]

(176) 0x41f178 MSUB	W5, W4, W21, W18

(176) 0x41f17c ADD	W6, W4, W25

(176) 0x41f180 SBFM	X30, X6, #0, #31

(176) 0x41f184 ADD	W8, W5, W20

(176) 0x41f188 SUB	W17, W22, W8

(176) 0x41f18c CMP	W1, W17

(176) 0x41f190 CSEL	X25, X1, X17, #9

(176) 0x41f194 ADD	W17, W18, W25

(176) 0x41f198 CMP	W18, W17

(176) 0x41f19c B.CS	41f29c

  (178) 0x41f1a0 LDR	X24, [X12]

  (178) 0x41f1a4 SBFM	X22, X8, #0, #31

  (178) 0x41f1a8 ADD	X18, X30, #1

  (178) 0x41f1ac ADD	X7, X22, #1

  (178) 0x41f1b0 MOVZ	X0, #0

  (178) 0x41f1b4 WHILELO	P0.D, XZR, X25

  (178) 0x41f1b8 LDR	X3, [X11]

  (178) 0x41f1bc LDR	X8, [X10]

  (178) 0x41f1c0 MADD	X2, X30, X24, X24

  (178) 0x41f1c4 LDR	X6, [X12, #16]

  (178) 0x41f1c8 MADD	X26, X30, X3, X22

  (178) 0x41f1cc LDR	X3, [X10, #16]

  (178) 0x41f1d0 SUB	X1, X2, X24

  (178) 0x41f1d4 ADD	X4, X2, X22

  (178) 0x41f1d8 MADD	X23, X30, X8, X22

  (178) 0x41f1dc ADD	X5, X1, X22

  (178) 0x41f1e0 LDR	X2, [X13]

  (178) 0x41f1e4 ADD	X1, X6, X4,LSL #3

  (178) 0x41f1e8 ADD	X8, X6, X5,LSL #3

  (178) 0x41f1ec ADD	X24, X3, X23,LSL #3

  (178) 0x41f1f0 LDR	X3, [X14]

  (178) 0x41f1f4 LDR	X23, [X13, #16]

  (178) 0x41f1f8 MADD	X4, X30, X2, XZR

  (178) 0x41f1fc ADD	X6, X4, X22

  (178) 0x41f200 ADD	X7, X7, X4

  (178) 0x41f204 ADD	X5, X23, X7,LSL #3

  (178) 0x41f208 ADD	X2, X23, X6,LSL #3

  (178) 0x41f20c MADD	X23, X30, X3, X22

  (178) 0x41f210 LDR	X30, [X11, #16]

  (178) 0x41f214 ADD	X22, X30, X26,LSL #3

  (178) 0x41f218 LDR	X26, [X14, #16]

  (178) 0x41f21c ADD	X4, X26, X23,LSL #3

    (177) 0x41f220 LD1D	{Z1.D}, P0/Z, [X4, X0,LSL #3]

    (177) 0x41f224 LD1D	{Z0.D}, P0/Z, [X5, X0,LSL #3]

    (177) 0x41f228 LD1D	{Z3.D}, P0/Z, [X2, X0,LSL #3]

    (177) 0x41f22c LD1D	{Z5.D}, P0/Z, [X8, X0,LSL #3]

    (177) 0x41f230 LD1D	{Z2.D}, P0/Z, [X1, X0,LSL #3]

    (177) 0x41f234 FADD	Z4.D, Z0.D, Z1.D

    (177) 0x41f238 FADD	Z6.D, Z5.D, Z3.D

    (177) 0x41f23c FSUB	Z7.D, Z4.D, Z6.D

    (177) 0x41f240 FADD	Z16.D, Z7.D, Z2.D

    (177) 0x41f244 ST1D	{Z16.D}, P0, [X22, X0,LSL #3]

    (177) 0x41f248 LD1D	{Z17.D}, P0/Z, [X2, X0,LSL #3]

    (177) 0x41f24c LD1D	{Z18.D}, P0/Z, [X5, X0,LSL #3]

    (177) 0x41f250 FSUB	Z19.D, Z17.D, Z18.D

    (177) 0x41f254 FADD	Z20.D, Z19.D, Z16.D

    (177) 0x41f258 ST1D	{Z20.D}, P0, [X24, X0,LSL #3]

    (177) 0x41f25c ADD	X0, X0, X9

    (177) 0x41f260 WHILELO	P0.D, X0, X25

    (177) 0x41f264 B.NE	41f220

  (178) 0x41f268 ADD	W25, W16, W18

  (178) 0x41f26c ORR	X30, XZR, X18

  (178) 0x41f270 CMP	W19, W25

  (178) 0x41f274 B.LE	41f2c0

  (178) 0x41f278 SUB	W1, W15, W17

  (178) 0x41f27c ORR	W18, WZR, W17

  (178) 0x41f280 ORR	W17, WZR, W21

  (178) 0x41f284 ORR	W8, WZR, W20

  (178) 0x41f288 CMP	W1, W17

  (178) 0x41f28c CSEL	X25, X1, X17, #9

  (178) 0x41f290 ADD	W17, W18, W25

  (178) 0x41f294 CMP	W18, W17

  (178) 0x41f298 B.CC	41f1a0

  (179) 0x41f29c ORR	W17, WZR, W18

  (179) 0x41f2a0 ADD	X18, X30, #1

  (179) 0x41f2a4 ADD	W25, W16, W18

  (179) 0x41f2a8 ORR	X30, XZR, X18

  (179) 0x41f2ac CMP	W19, W25

  (179) 0x41f2b0 B.GT	41f278

(176) 0x41f2b4 HINT	#0

(176) 0x41f2b8 HINT	#0

(176) 0x41f2bc HINT	#0

(176) 0x41f2c0 LDP	X21, X22, [SP, #32]

(176) 0x41f2c4 LDP	X23, X24, [SP, #48]

(176) 0x41f2c8 LDP	X19, X20, [SP, #16]

(176) 0x41f2cc LDP	X25, X26, [SP, #64]

(176) 0x41f2d0 LDP	X29, X30, [SP], #80

(176) 0x41f2d4 RET

(176) 0x41f2d8 ADD	W1, W1, #1

(176) 0x41f2dc MOVZ	W0, #0

(176) 0x41f2e0 B	41f150

0x41f2e4 LDP	X21, X22, [SP, #32]

0x41f2e8 B	41f2c8

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.66 cycles (7.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f0e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f2c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f2e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f2d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 41f2c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	3.00	3.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f0e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W20, W3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f2c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W22, W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 41f2e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD W26, W26, W21, WZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41f2d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 41f2c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.76	0.17
▼Loop 176 - advec_cell.cpp:44-48 - exec–	0	0
▼Loop 178 - advec_cell.cpp:46-48 - exec–	0.04	0.01
○Loop 177 - advec_cell.cpp:47-48 - exec	0.72	0.17
○Loop 179 - advec_cell.cpp:48-48 - exec	0	0

Report Configuration

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code