OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage: 5.07%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

0x41ea40 STP	X29, X30, [SP, #800]!

0x41ea44 ADD	X29, SP, #0

0x41ea48 STP	X19, X20, [SP, #16]

0x41ea4c ORR	X20, XZR, X0

0x41ea50 STP	X21, X22, [SP, #32]

0x41ea54 LDP	W22, W1, [X0, #96]

0x41ea58 LDR	W0, [X0, #88]

0x41ea5c LDR	W4, [X20, #92]

0x41ea60 ADD	W2, W1, #3

0x41ea64 ADD	W22, W22, #1

0x41ea68 ADD	W3, W0, #1

0x41ea6c STP	W2, W3, [SP, #192]

0x41ea70 CMP	W22, W2

0x41ea74 B.GE	41eeac

0x41ea78 ADD	W19, W4, #3

0x41ea7c STP	X23, X24, [SP, #48]

0x41ea80 SUB	W23, W2, W22

0x41ea84 CMP	W3, W19

0x41ea88 B.GE	41eebc

0x41ea8c SUB	W5, W19, W3

0x41ea90 MADD	W24, W23, W5, WZR

0x41ea94 STR	W5, [SP, #200]

0x41ea98 BL	403530

0x41ea9c ORR	W21, WZR, W0

0x41eaa0 BL	4033c0

0x41eaa4 UDIV	W7, W24, W21

0x41eaa8 ORR	W6, WZR, W0

0x41eaac MSUB	W8, W7, W21, W24

0x41eab0 CMP	W0, W8

0x41eab4 B.CC	41eed0

  (169) 0x41eab8 MADD	W24, W7, W6, W8

  (169) 0x41eabc ADD	W9, W7, W24

  (169) 0x41eac0 STR	W9, [SP, #204]

  (169) 0x41eac4 CMP	W24, W9

  (169) 0x41eac8 B.CS	41eebc

(171) 0x41eacc LDR	W10, [SP, #200]

(171) 0x41ead0 FMOV	D0, #4.0000000

(171) 0x41ead4 PTRUE	P1.B, ALL

(171) 0x41ead8 STP	X25, X26, [SP, #64]

(171) 0x41eadc LDR	W16, [SP, #196]

(171) 0x41eae0 UDIV	W11, W24, W10

(171) 0x41eae4 STP	X27, X28, [SP, #80]

(171) 0x41eae8 CNTD	X28, ALL

(171) 0x41eaec LDR	X25, [X20, #16]

(171) 0x41eaf0 LDR	X13, [X20]

(171) 0x41eaf4 LDR	X17, [X20, #8]

(171) 0x41eaf8 STR	X25, [SP, #104]

(171) 0x41eafc LDR	X27, [X20, #24]

(171) 0x41eb00 MSUB	W12, W11, W10, W24

(171) 0x41eb04 ADD	W30, W11, W22

(171) 0x41eb08 STR	X13, [SP, #112]

(171) 0x41eb0c LDR	X22, [X20, #32]

(171) 0x41eb10 SBFM	X15, X30, #0, #31

(171) 0x41eb14 STR	X17, [SP, #144]

(171) 0x41eb18 LDR	X14, [X20, #40]

(171) 0x41eb1c ADD	W23, W12, W16

(171) 0x41eb20 SUB	W25, W19, W23

(171) 0x41eb24 STR	X27, [SP, #208]

(171) 0x41eb28 LDR	X18, [X20, #48]

(171) 0x41eb2c CMP	W7, W25

(171) 0x41eb30 CSEL	W4, W7, W25, #9

(171) 0x41eb34 ADD	W3, W24, W4

(171) 0x41eb38 STR	X22, [SP, #120]

(171) 0x41eb3c LDR	X26, [X20, #56]

(171) 0x41eb40 STR	W3, [SP, #100]

(171) 0x41eb44 LDR	X0, [X20, #64]

(171) 0x41eb48 STR	X14, [SP, #160]

(171) 0x41eb4c LDR	D3, [X20, #80]

(171) 0x41eb50 STR	X26, [SP, #136]

(171) 0x41eb54 LDR	X20, [X20, #72]

(171) 0x41eb58 STR	X0, [SP, #128]

(171) 0x41eb5c STR	X18, [SP, #216]

(171) 0x41eb60 FMUL	D1, D3, D0

(171) 0x41eb64 DUP	Z16.D, Z1.D[0]

(171) 0x41eb68 STR	X20, [SP, #152]

(171) 0x41eb6c CMP	W24, W3

(171) 0x41eb70 B.CS	41ee7c

(171) 0x41eb74 HINT	#0

(171) 0x41eb78 HINT	#0

(171) 0x41eb7c HINT	#0

  (172) 0x41eb80 LDP	X13, X21, [SP, #136]

  (172) 0x41eb84 SUB	W2, W30, #1

  (172) 0x41eb88 SBFM	X1, X23, #0, #31

  (172) 0x41eb8c SBFM	X6, X2, #0, #31

  (172) 0x41eb90 ORR	W4, WZR, W4

  (172) 0x41eb94 WHILELO	P0.D, XZR, X4

  (172) 0x41eb98 LDP	X19, X5, [SP, #104]

  (172) 0x41eb9c LDP	X24, X12, [SP, #120]

  (172) 0x41eba0 LDR	X7, [SP, #160]

  (172) 0x41eba4 LDR	X16, [SP, #208]

  (172) 0x41eba8 LDR	X27, [X21]

  (172) 0x41ebac LDR	X23, [X19]

  (172) 0x41ebb0 LDR	X10, [X24]

  (172) 0x41ebb4 MADD	X3, X15, X27, X1

  (172) 0x41ebb8 LDR	X14, [X7]

  (172) 0x41ebbc MADD	X8, X6, X23, X1

  (172) 0x41ebc0 LDR	X24, [X16]

  (172) 0x41ebc4 UBFM	X27, X3, #61, #60

  (172) 0x41ebc8 MADD	X9, X23, X15, X1

  (172) 0x41ebcc MADD	X0, X6, X10, X1

  (172) 0x41ebd0 LDR	X2, [X5]

  (172) 0x41ebd4 UBFM	X17, X8, #61, #60

  (172) 0x41ebd8 MADD	X20, X10, X15, X1

  (172) 0x41ebdc MADD	X18, X6, X14, X1

  (172) 0x41ebe0 UBFM	X11, X9, #61, #60

  (172) 0x41ebe4 SUB	X23, X17, #8

  (172) 0x41ebe8 MADD	X25, X14, X15, X1

  (172) 0x41ebec UBFM	X8, X0, #61, #60

  (172) 0x41ebf0 SUB	X22, X11, #8

  (172) 0x41ebf4 MADD	X19, X6, X24, X1

  (172) 0x41ebf8 UBFM	X10, X20, #61, #60

  (172) 0x41ebfc LDR	X13, [X13]

  (172) 0x41ec00 MADD	X21, X24, X15, X1

  (172) 0x41ec04 UBFM	X7, X18, #61, #60

  (172) 0x41ec08 SUB	X14, X8, #8

  (172) 0x41ec0c MADD	X3, X6, X2, X1

  (172) 0x41ec10 LDR	X6, [X12]

  (172) 0x41ec14 UBFM	X26, X25, #61, #60

  (172) 0x41ec18 UBFM	X0, X19, #61, #60

  (172) 0x41ec1c MADD	X5, X2, X15, X1

  (172) 0x41ec20 LDR	X12, [X16, #16]

  (172) 0x41ec24 SUB	X25, X0, #8

  (172) 0x41ec28 UBFM	X9, X21, #61, #60

  (172) 0x41ec2c LDP	X16, X21, [SP, #104]

  (172) 0x41ec30 SUB	X20, X9, #8

  (172) 0x41ec34 MADD	X2, X15, X6, X1

  (172) 0x41ec38 ADD	X19, X12, X0

  (172) 0x41ec3c LDR	X0, [SP, #216]

  (172) 0x41ec40 ADD	X24, X12, X20

  (172) 0x41ec44 ADD	X18, X12, X9

  (172) 0x41ec48 ADD	X25, X12, X25

  (172) 0x41ec4c MADD	X20, X15, X13, X1

  (172) 0x41ec50 LDR	X9, [X16, #16]

  (172) 0x41ec54 SUB	X13, X7, #8

  (172) 0x41ec58 ORR	X6, XZR, X0

  (172) 0x41ec5c LDR	X0, [X0, #16]

  (172) 0x41ec60 LDR	X12, [X6]

  (172) 0x41ec64 ADD	X16, X9, X11

  (172) 0x41ec68 ADD	X23, X9, X23

  (172) 0x41ec6c ADD	X17, X9, X17

  (172) 0x41ec70 ADD	X22, X9, X22

  (172) 0x41ec74 LDR	X9, [X21, #16]

  (172) 0x41ec78 SUB	X11, X26, #8

  (172) 0x41ec7c STP	X0, X5, [SP, #168]

  (172) 0x41ec80 SUB	X0, X10, #8

  (172) 0x41ec84 MADD	X21, X15, X12, X1

  (172) 0x41ec88 LDR	X12, [SP, #120]

  (172) 0x41ec8c ADD	X3, X9, X3,LSL #3

  (172) 0x41ec90 LDR	X5, [SP, #152]

  (172) 0x41ec94 LDR	X6, [X5]

  (172) 0x41ec98 LDR	X5, [X12, #16]

  (172) 0x41ec9c MADD	X1, X15, X6, X1

  (172) 0x41eca0 ADD	X12, X5, X0

  (172) 0x41eca4 LDR	X0, [SP, #160]

  (172) 0x41eca8 ADD	X6, X5, X10

  (172) 0x41ecac ADD	X14, X5, X14

  (172) 0x41ecb0 ADD	X8, X5, X8

  (172) 0x41ecb4 SUB	X10, X27, #8

  (172) 0x41ecb8 LDR	X5, [X0, #16]

  (172) 0x41ecbc LDR	X0, [SP, #128]

  (172) 0x41ecc0 ADD	X13, X5, X13

  (172) 0x41ecc4 ADD	X7, X5, X7

  (172) 0x41ecc8 ADD	X11, X5, X11

  (172) 0x41eccc ADD	X5, X5, X26

  (172) 0x41ecd0 LDR	X26, [SP, #144]

  (172) 0x41ecd4 LDR	X0, [X0, #16]

  (172) 0x41ecd8 LDR	X26, [X26, #16]

  (172) 0x41ecdc STR	X0, [SP, #184]

  (172) 0x41ece0 LDR	X0, [SP, #176]

  (172) 0x41ece4 ADD	X10, X26, X10

  (172) 0x41ece8 ADD	X27, X26, X27

  (172) 0x41ecec LDR	X26, [SP, #136]

  (172) 0x41ecf0 ADD	X9, X9, X0,LSL #3

  (172) 0x41ecf4 LDR	X0, [X26, #16]

  (172) 0x41ecf8 LDR	X26, [SP, #168]

  (172) 0x41ecfc STR	X0, [SP, #176]

  (172) 0x41ed00 LDR	X0, [SP, #184]

  (172) 0x41ed04 ADD	X21, X26, X21,LSL #3

  (172) 0x41ed08 LDR	X26, [SP, #152]

  (172) 0x41ed0c ADD	X2, X0, X2,LSL #3

  (172) 0x41ed10 LDR	X0, [X26, #16]

  (172) 0x41ed14 LDR	X26, [SP, #176]

  (172) 0x41ed18 STR	X0, [SP, #168]

  (172) 0x41ed1c LDR	X0, [SP, #168]

  (172) 0x41ed20 ADD	X20, X26, X20,LSL #3

  (172) 0x41ed24 MOVZ	X26, #0

  (172) 0x41ed28 ADD	X1, X0, X1,LSL #3

    (170) 0x41ed2c LD1D	{Z2.D}, P0/Z, [X24, X26,LSL #3]

    (170) 0x41ed30 LD1D	{Z5.D}, P0/Z, [X22, X26,LSL #3]

    (170) 0x41ed34 LD1D	{Z4.D}, P0/Z, [X25, X26,LSL #3]

    (170) 0x41ed38 LD1D	{Z17.D}, P0/Z, [X19, X26,LSL #3]

    (170) 0x41ed3c LD1D	{Z7.D}, P0/Z, [X23, X26,LSL #3]

    (170) 0x41ed40 FMUL	Z6.D, Z5.D, Z2.D

    (170) 0x41ed44 FMAD	Z7.D, P1/M, Z4.D, Z6.D

    (170) 0x41ed48 LD1D	{Z18.D}, P0/Z, [X17, X26,LSL #3]

    (170) 0x41ed4c LD1D	{Z19.D}, P0/Z, [X18, X26,LSL #3]

    (170) 0x41ed50 LD1D	{Z22.D}, P0/Z, [X12, X26,LSL #3]

    (170) 0x41ed54 LD1D	{Z23.D}, P0/Z, [X6, X26,LSL #3]

    (170) 0x41ed58 LD1D	{Z26.D}, P0/Z, [X9, X26,LSL #3]

    (170) 0x41ed5c LD1D	{Z27.D}, P0/Z, [X14, X26,LSL #3]

    (170) 0x41ed60 LD1D	{Z29.D}, P0/Z, [X8, X26,LSL #3]

    (170) 0x41ed64 LD1D	{Z30.D}, P0/Z, [X3, X26,LSL #3]

    (170) 0x41ed68 LD1D	{Z0.D}, P0/Z, [X21, X26,LSL #3]

    (170) 0x41ed6c LD1D	{Z21.D}, P0/Z, [X16, X26,LSL #3]

    (170) 0x41ed70 FMUL	Z20.D, Z18.D, Z17.D

    (170) 0x41ed74 FSUB	Z25.D, Z22.D, Z23.D

    (170) 0x41ed78 FMAD	Z21.D, P1/M, Z19.D, Z20.D

    (170) 0x41ed7c FMUL	Z28.D, Z25.D, Z26.D

    (170) 0x41ed80 FADD	Z24.D, Z7.D, Z21.D

    (170) 0x41ed84 FSUB	Z31.D, Z27.D, Z29.D

    (170) 0x41ed88 FDIVR	Z24.D, P1/M, Z24.D, Z16.D

    (170) 0x41ed8c FMAD	Z31.D, P1/M, Z30.D, Z28.D

    (170) 0x41ed90 FMAD	Z31.D, P1/M, Z24.D, Z0.D

    (170) 0x41ed94 ST1D	{Z31.D}, P0, [X2, X26,LSL #3]

    (170) 0x41ed98 LD1D	{Z3.D}, P0/Z, [X8, X26,LSL #3]

    (170) 0x41ed9c LD1D	{Z1.D}, P0/Z, [X6, X26,LSL #3]

    (170) 0x41eda0 LD1D	{Z5.D}, P0/Z, [X27, X26,LSL #3]

    (170) 0x41eda4 LD1D	{Z6.D}, P0/Z, [X14, X26,LSL #3]

    (170) 0x41eda8 LD1D	{Z4.D}, P0/Z, [X12, X26,LSL #3]

    (170) 0x41edac LD1D	{Z17.D}, P0/Z, [X10, X26,LSL #3]

    (170) 0x41edb0 FSUB	Z2.D, Z3.D, Z1.D

    (170) 0x41edb4 FMUL	Z7.D, Z2.D, Z5.D

    (170) 0x41edb8 LD1D	{Z19.D}, P0/Z, [X20, X26,LSL #3]

    (170) 0x41edbc FSUB	Z18.D, Z6.D, Z4.D

    (170) 0x41edc0 FMAD	Z18.D, P1/M, Z17.D, Z7.D

    (170) 0x41edc4 FMAD	Z18.D, P1/M, Z24.D, Z19.D

    (170) 0x41edc8 ST1D	{Z18.D}, P0, [X1, X26,LSL #3]

    (170) 0x41edcc LD1D	{Z20.D}, P0/Z, [X2, X26,LSL #3]

    (170) 0x41edd0 LD1D	{Z21.D}, P0/Z, [X3, X26,LSL #3]

    (170) 0x41edd4 LD1D	{Z22.D}, P0/Z, [X13, X26,LSL #3]

    (170) 0x41edd8 LD1D	{Z23.D}, P0/Z, [X7, X26,LSL #3]

    (170) 0x41eddc LD1D	{Z25.D}, P0/Z, [X9, X26,LSL #3]

    (170) 0x41ede0 LD1D	{Z27.D}, P0/Z, [X11, X26,LSL #3]

    (170) 0x41ede4 FSUB	Z26.D, Z22.D, Z23.D

    (170) 0x41ede8 LD1D	{Z28.D}, P0/Z, [X5, X26,LSL #3]

    (170) 0x41edec FSUB	Z29.D, Z27.D, Z28.D

    (170) 0x41edf0 FMUL	Z30.D, Z29.D, Z25.D

    (170) 0x41edf4 FMAD	Z26.D, P1/M, Z21.D, Z30.D

    (170) 0x41edf8 FMAD	Z26.D, P1/M, Z24.D, Z20.D

    (170) 0x41edfc ST1D	{Z26.D}, P0, [X2, X26,LSL #3]

    (170) 0x41ee00 LD1D	{Z31.D}, P0/Z, [X7, X26,LSL #3]

    (170) 0x41ee04 LD1D	{Z0.D}, P0/Z, [X5, X26,LSL #3]

    (170) 0x41ee08 LD1D	{Z3.D}, P0/Z, [X27, X26,LSL #3]

    (170) 0x41ee0c LD1D	{Z1.D}, P0/Z, [X13, X26,LSL #3]

    (170) 0x41ee10 LD1D	{Z6.D}, P0/Z, [X11, X26,LSL #3]

    (170) 0x41ee14 LD1D	{Z7.D}, P0/Z, [X10, X26,LSL #3]

    (170) 0x41ee18 LD1D	{Z4.D}, P0/Z, [X1, X26,LSL #3]

    (170) 0x41ee1c FSUB	Z5.D, Z31.D, Z0.D

    (170) 0x41ee20 FSUB	Z17.D, Z1.D, Z6.D

    (170) 0x41ee24 FMUL	Z2.D, Z5.D, Z3.D

    (170) 0x41ee28 FMAD	Z17.D, P1/M, Z7.D, Z2.D

    (170) 0x41ee2c FMAD	Z24.D, P1/M, Z17.D, Z4.D

    (170) 0x41ee30 ST1D	{Z24.D}, P0, [X1, X26,LSL #3]

    (170) 0x41ee34 ADD	X26, X26, X28

    (170) 0x41ee38 WHILELO	P0.D, X26, X4

    (170) 0x41ee3c B.NE	41ed2c

  (172) 0x41ee40 LDR	W4, [SP, #192]

  (172) 0x41ee44 ADD	W30, W30, #1

  (172) 0x41ee48 ADD	X15, X15, #1

  (172) 0x41ee4c CMP	W4, W30

  (172) 0x41ee50 B.LE	41eea0

  (172) 0x41ee54 LDR	W24, [SP, #100]

  (172) 0x41ee58 LDR	W19, [SP, #204]

  (172) 0x41ee5c LDP	W23, W25, [SP, #196]

  (172) 0x41ee60 SUB	W7, W19, W24

  (172) 0x41ee64 CMP	W7, W25

  (172) 0x41ee68 CSEL	W4, W7, W25, #9

  (172) 0x41ee6c ADD	W3, W24, W4

  (172) 0x41ee70 STR	W3, [SP, #100]

  (172) 0x41ee74 CMP	W24, W3

  (172) 0x41ee78 B.CC	41eb80

  (173) 0x41ee7c LDR	W4, [SP, #192]

  (173) 0x41ee80 ADD	W30, W30, #1

  (173) 0x41ee84 ADD	X15, X15, #1

  (173) 0x41ee88 STR	W24, [SP, #100]

  (173) 0x41ee8c CMP	W4, W30

  (173) 0x41ee90 B.GT	41ee54

(171) 0x41ee94 HINT	#0

(171) 0x41ee98 HINT	#0

(171) 0x41ee9c HINT	#0

(171) 0x41eea0 LDP	X23, X24, [SP, #48]

(171) 0x41eea4 LDP	X25, X26, [SP, #64]

(171) 0x41eea8 LDP	X27, X28, [SP, #80]

(171) 0x41eeac LDP	X19, X20, [SP, #16]

(171) 0x41eeb0 LDP	X21, X22, [SP, #32]

(171) 0x41eeb4 LDP	X29, X30, [SP], #224

(171) 0x41eeb8 RET

  (169) 0x41eebc LDP	X19, X20, [SP, #16]

  (169) 0x41eec0 LDP	X21, X22, [SP, #32]

  (169) 0x41eec4 LDP	X23, X24, [SP, #48]

  (169) 0x41eec8 LDP	X29, X30, [SP], #224

  (169) 0x41eecc RET

  (169) 0x41eed0 ADD	W7, W7, #1

  (169) 0x41eed4 MOVZ	W8, #0

  (169) 0x41eed8 B	41eab8

0x41eedc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp:40-53

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.75 to 0.62 cycles (7.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41ea40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #800]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W1, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [X20, #92]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W2, W3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41eeac <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W23, W2, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41eebc <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W5, W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W24, W23, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41eed0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp:40-53

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41ea40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #800]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W22, W1, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [X20, #92]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W2, W3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W22, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41eeac <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W23, W2, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41eebc <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W5, W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W24, W23, W5, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41eed0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.07	1.16
▼Loop 171 - accelerate.cpp:40-53 - exec–	0	0
▼Loop 172 - accelerate.cpp:42-53 - exec–	0.04	0.01
○Loop 170 - accelerate.cpp:43-53 - exec	5.03	1.15
○Loop 169 - accelerate.cpp:40-42 - exec	0	0
○Loop 173 - accelerate.cpp:42-42 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code