OV - exec - Loop 244

	Loop Id: 244	Module: exec	Source: advec_mom.cpp:169-172 [...]	Coverage: 0.01%

0x421400 LDR	X8, [X22]

0x421404 SUB	W6, W16, #1

0x421408 SBFM	X12, X7, #0, #31

0x42140c SBFM	X13, X6, #0, #31

0x421410 MOVZ	X0, #0

0x421414 WHILELO	P0.D, XZR, X1

0x421418 LDR	X18, [X22, #16]

0x42141c LDR	X6, [X27]

0x421420 MADD	X7, X13, X8, X12

0x421424 MADD	X10, X14, X8, X12

0x421428 LDR	X2, [X23]

0x42142c UBFM	X17, X7, #61, #60

0x421430 LDR	X4, [X25]

0x421434 UBFM	X3, X10, #61, #60

0x421438 SUB	X11, X17, #8

0x42143c MADD	X8, X13, X6, X12

0x421440 SUB	X19, X3, #8

0x421444 ADD	X7, X18, X17

0x421448 LDR	X17, [X26]

0x42144c ADD	X10, X18, X19

0x421450 ADD	X5, X18, X3

0x421454 MADD	X19, X14, X6, X12

0x421458 LDR	X3, [X27, #16]

0x42145c MADD	X9, X14, X2, X12

0x421460 UBFM	X2, X8, #61, #60

0x421464 ADD	X11, X18, X11

0x421468 MADD	X18, X14, X4, X12

0x42146c UBFM	X6, X19, #61, #60

0x421470 MADD	X4, X13, X17, X12

0x421474 SUB	X13, X2, #8

0x421478 MADD	X17, X17, X14, X12

0x42147c SUB	X12, X6, #8

0x421480 ADD	X8, X3, X2

0x421484 ADD	X13, X3, X13

0x421488 ADD	X12, X3, X12

0x42148c ADD	X6, X3, X6

0x421490 LDR	X3, [X23, #16]

0x421494 ADD	X19, X3, X9,LSL #3

0x421498 LDR	X9, [X26, #16]

0x42149c ADD	X2, X9, X4,LSL #3

0x4214a0 ADD	X4, X9, X17,LSL #3

0x4214a4 LDR	X17, [X25, #16]

0x4214a8 ADD	X18, X17, X18,LSL #3

  (243) 0x4214ac LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

  (243) 0x4214b0 LD1D	{Z1.D}, P0/Z, [X5, X0,LSL #3]

  (243) 0x4214b4 LD1D	{Z2.D}, P0/Z, [X8, X0,LSL #3]

  (243) 0x4214b8 LD1D	{Z6.D}, P0/Z, [X7, X0,LSL #3]

  (243) 0x4214bc LD1D	{Z4.D}, P0/Z, [X12, X0,LSL #3]

  (243) 0x4214c0 LD1D	{Z7.D}, P0/Z, [X10, X0,LSL #3]

  (243) 0x4214c4 LD1D	{Z16.D}, P0/Z, [X13, X0,LSL #3]

  (243) 0x4214c8 LD1D	{Z18.D}, P0/Z, [X11, X0,LSL #3]

  (243) 0x4214cc FMUL	Z3.D, Z1.D, Z0.D

  (243) 0x4214d0 FMUL	Z17.D, Z7.D, Z4.D

  (243) 0x4214d4 FMAD	Z6.D, P1/M, Z2.D, Z3.D

  (243) 0x4214d8 FMAD	Z18.D, P1/M, Z16.D, Z17.D

  (243) 0x4214dc FADD	Z19.D, Z6.D, Z18.D

  (243) 0x4214e0 FMUL	Z20.D, Z19.D, Z5.D

  (243) 0x4214e4 ST1D	{Z20.D}, P0, [X18, X0,LSL #3]

  (243) 0x4214e8 LD1D	{Z21.D}, P0/Z, [X2, X0,LSL #3]

  (243) 0x4214ec LD1D	{Z22.D}, P0/Z, [X4, X0,LSL #3]

  (243) 0x4214f0 FSUB	Z23.D, Z22.D, Z21.D

  (243) 0x4214f4 FADD	Z24.D, Z23.D, Z20.D

  (243) 0x4214f8 ST1D	{Z24.D}, P0, [X19, X0,LSL #3]

  (243) 0x4214fc ADD	X0, X0, X15

  (243) 0x421500 WHILELO	P0.D, X0, X1

  (243) 0x421504 B.NE	4214ac

0x421508 ADD	W16, W16, #1

0x42150c ADD	X14, X14, #1

0x421510 CMP	W20, W16

0x421514 B.LE	421550

0x421518 SUB	W1, W28, W30

0x42151c ORR	W11, WZR, W30

0x421520 ORR	W30, WZR, W24

0x421524 ORR	W7, WZR, W21

0x421528 CMP	W1, W30

0x42152c CSEL	X1, X1, X30, #9

0x421530 ADD	W30, W11, W1

0x421534 CMP	W11, W30

0x421538 B.CC	421400

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 169 - 172

--------------------------------------------------------------------------------

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.82+	__kmp_GOMP_microtask_wrapper(i[...]		libomp.so
○	__kmp_invoke_microtask		libomp.so
►1.18+	GOMP_parallel		libomp.so
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:167	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:244	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:906	exec
○	main	iostream:74	exec
○	__libc_start_main		libc-2.31.so
○	_start	iostream:74	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.9]
Source	advec_mom.cpp:169-172,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	2.13
Front-end cycles	7.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	11.00
P2 cycles	11.00
P3 cycles	11.00
P4 cycles	11.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.27
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.9]
Source	advec_mom.cpp:169-172,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	2.13
Front-end cycles	7.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	11.00
P2 cycles	11.00
P3 cycles	11.00
P4 cycles	11.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.27
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.9]
Source file and lines	advec_mom.cpp:169-172
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:169-172
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.12 cycles (5.18x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00
cycles	1.00	1.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Overall L1	11.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

7% of peak load performance is reached (7.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421518

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W6, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X13, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X1	1	0	0	0	0	1	0	0	0	0	3	2
LDR X18, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X7, X13, X8, X12	1	0	0	0	0	1	0	0	0	0	2	1
MADD X10, X14, X8, X12	1	0	0	0	0	1	0	0	0	0	2	1
LDR X2, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X17, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X4, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X3, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X11, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X8, X13, X6, X12	1	0	0	0	0	1	0	0	0	0	2	1
SUB X19, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X10, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X19, X14, X6, X12	1	0	0	0	0	1	0	0	0	0	2	1
LDR X3, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X9, X14, X2, X12	1	0	0	0	0	1	0	0	0	0	2	1
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X11, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X18, X14, X4, X12	1	0	0	0	0	1	0	0	0	0	2	1
UBFM X6, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X4, X13, X17, X12	1	0	0	0	0	1	0	0	0	0	2	1
SUB X13, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X17, X17, X14, X12	1	0	0	0	0	1	0	0	0	0	2	1
SUB X12, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X13, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X12, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X19, X3, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X2, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X9, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W20, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 421550 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W1, W28, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W11, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W30, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W1, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X1, X1, X30, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W30, W11, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W11, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 421400 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.9]
Source file and lines	advec_mom.cpp:169-172
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:169-172
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00
cycles	1.00	1.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Overall L1	11.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

7% of peak load performance is reached (7.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421518

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W6, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X13, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X1	1	0	0	0	0	1	0	0	0	0	3	2
LDR X18, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X7, X13, X8, X12	1	0	0	0	0	1	0	0	0	0	2	1
MADD X10, X14, X8, X12	1	0	0	0	0	1	0	0	0	0	2	1
LDR X2, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X17, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X4, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X3, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X11, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X8, X13, X6, X12	1	0	0	0	0	1	0	0	0	0	2	1
SUB X19, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X10, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X19, X14, X6, X12	1	0	0	0	0	1	0	0	0	0	2	1
LDR X3, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X9, X14, X2, X12	1	0	0	0	0	1	0	0	0	0	2	1
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X11, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X18, X14, X4, X12	1	0	0	0	0	1	0	0	0	0	2	1
UBFM X6, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X4, X13, X17, X12	1	0	0	0	0	1	0	0	0	0	2	1
SUB X13, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X17, X17, X14, X12	1	0	0	0	0	1	0	0	0	0	2	1
SUB X12, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X13, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X12, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X19, X3, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X2, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X9, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W20, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 421550 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W1, W28, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W11, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W30, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W1, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X1, X1, X30, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W30, W11, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W11, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 421400 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code