OV - exec - Loop 321

0x41da08 MOVPRFX	Z18, Z0

0x41da0c SDIV	Z18.D, P0/M, Z18.D, Z2.D

0x41da10 ADD	Z19.D, Z3.D, Z18.D

0x41da14 MSB	Z18.D, P0/M, Z2.D, Z0.D

0x41da18 ADD	Z0.D, Z0.D, Z1.D

0x41da1c SUBS	X12, X12, X10

0x41da20 SXTW	Z19.D, P0/M, Z19.D

0x41da24 MOVPRFX	Z25, Z16

0x41da28 MUL	Z25.D, P0/M, Z25.D, Z19.D

0x41da2c ADD	Z20.D, Z4.D, Z18.D

0x41da30 ADD	Z18.D, Z7.D, Z18.D

0x41da34 MOVPRFX	Z21, Z20

0x41da38 SXTW	Z21.D, P0/M, Z20.D

0x41da3c MOVPRFX	Z22, Z21

0x41da40 MLA	Z22.D, P0/M, Z5.D, Z19.D

0x41da44 LD1D	{Z23.D}, P0/Z, [X23, Z22.D,LSL #3]    [5]

0x41da48 MOVPRFX	Z24, Z21

0x41da4c MLA	Z24.D, P0/M, Z6.D, Z19.D

0x41da50 LD1D	{Z24.D}, P0/Z, [X25, Z24.D,LSL #3]    [3]

0x41da54 MAD	Z19.D, P0/M, Z17.D, Z21.D

0x41da58 ADR	Z18.D, [Z25, Z18.D,SXTW]    [7]

0x41da5c ADR	Z20.D, [Z25, Z20.D,SXTW]    [1]

0x41da60 LD1D	{Z18.D}, P0/Z, [X27, Z18.D,LSL #3]    [2]

0x41da64 LD1D	{Z20.D}, P0/Z, [X27, Z20.D,LSL #3]    [4]

0x41da68 LD1D	{Z19.D}, P0/Z, [X19, Z19.D,LSL #3]    [6]

0x41da6c FMLA	Z18.D, P0/M, Z24.D, Z23.D

0x41da70 FSUB	Z18.D, Z18.D, Z20.D

0x41da74 FDIV	Z18.D, P0/M, Z18.D, Z19.D

0x41da78 ST1D	{Z18.D}, P0, [X23, Z22.D,LSL #3]    [5]

0x41da7c B.NE	41da08

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 147 - 149

--------------------------------------------------------------------------------

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.93
Bottlenecks	P6, P7,
Function	.omp_outlined..14#0x41d8d0
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	10.25
Front-end cycles	3.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.00
P6 cycles	11.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.45
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	72.41
Vectorization ratio load	71.43
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	70.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	92.24
Vector-efficiency ratio load	78.57
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	77.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.93
Bottlenecks	P6, P7,
Function	.omp_outlined..14#0x41d8d0
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	10.25
Front-end cycles	3.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.00
P6 cycles	11.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.45
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	72.41
Vectorization ratio load	71.43
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	70.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	92.24
Vector-efficiency ratio load	78.57
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	77.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..14#0x41d8d0
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 92% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.00 to 10.25 cycles (1.07x speedup).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

71% of VPU loads are used in vector version.
70% of VPU addition or subtraction instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)
4: divide

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	0.50	0.50	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	1.00	1.00	3.00	3.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

INT

all	69%
load	71%
store	100%
mul	100%
add-sub	66%
fma	100%
other	37%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	72%
load	71%
store	100%
mul	100%
add-sub	70%
fma	100%
div/sqrt	100%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

15% of peak load performance is reached (14.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41da08

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z18.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z25, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z25.D, P0/M, Z25.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z21.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z5.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z24, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z24.D}, P0/Z, [X25, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z18.D, [Z25, Z18.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z20.D, [Z25, Z20.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X27, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X27, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z18.D, P0/M, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z18.D, P0/M, Z18.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z18.D}, P0, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41da08 <.omp_outlined..14+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..14#0x41d8d0
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 92% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.00 to 10.25 cycles (1.07x speedup).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

71% of VPU loads are used in vector version.
70% of VPU addition or subtraction instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)
4: divide

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	0.50	0.50	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	1.00	1.00	3.00	3.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

INT

all	69%
load	71%
store	100%
mul	100%
add-sub	66%
fma	100%
other	37%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	72%
load	71%
store	100%
mul	100%
add-sub	70%
fma	100%
div/sqrt	100%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

15% of peak load performance is reached (14.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41da08

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z18.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z25, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z25.D, P0/M, Z25.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z21.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z5.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z24, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z24.D}, P0/Z, [X25, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z18.D, [Z25, Z18.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z20.D, [Z25, Z20.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X27, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X27, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z18.D, P0/M, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z18.D, P0/M, Z18.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z18.D}, P0, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41da08 <.omp_outlined..14+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code