OV - exec - Loop 304

	Loop Id: 304	Module: exec	Source: advec_mom.cpp:109-139 [...]	Coverage: 3.68%

0x41d660 MOVPRFX	Z23, Z0

0x41d664 SDIV	Z23.D, P0/M, Z23.D, Z2.D

0x41d668 ADD	Z24.D, Z3.D, Z23.D

0x41d66c MSB	Z23.D, P0/M, Z2.D, Z0.D

0x41d670 ADD	Z0.D, Z0.D, Z1.D

0x41d674 SUBS	X12, X12, X10

0x41d678 SXTW	Z24.D, P0/M, Z24.D

0x41d67c MOVPRFX	Z9, Z7

0x41d680 MUL	Z9.D, P0/M, Z9.D, Z24.D

0x41d684 ADD	Z25.D, Z4.D, Z23.D

0x41d688 MOVPRFX	Z26, Z25

0x41d68c SXTW	Z26.D, P0/M, Z25.D

0x41d690 MOVPRFX	Z27, Z26

0x41d694 MLA	Z27.D, P0/M, Z5.D, Z24.D

0x41d698 LD1D	{Z27.D}, P0/Z, [X23, Z27.D,LSL #3]    [7]

0x41d69c ADD	Z28.D, Z17.D, Z23.D

0x41d6a0 ADD	Z30.D, Z18.D, Z23.D

0x41d6a4 ADD	Z23.D, Z19.D, Z23.D

0x41d6a8 MOVPRFX	Z29, Z28

0x41d6ac SXTW	Z29.D, P0/M, Z28.D

0x41d6b0 MOVPRFX	Z8, Z27

0x41d6b4 FABS	Z8.D, P0/M, Z27.D

0x41d6b8 FCMLT	P1.D, P0/Z, Z27.D, #0

0x41d6bc SEL	Z31.D, P1, Z26.D, Z29.D

0x41d6c0 SEL	Z29.D, P1, Z29.D, Z26.D

0x41d6c4 SEL	Z23.D, P1, Z23.D, Z30.D

0x41d6c8 SEL	Z28.D, P1, Z28.D, Z30.D

0x41d6cc MOVPRFX	Z30, Z29

0x41d6d0 MLA	Z30.D, P0/M, Z6.D, Z24.D

0x41d6d4 LD1D	{Z30.D}, P0/Z, [X25, Z30.D,LSL #3]    [5]

0x41d6d8 MAD	Z24.D, P0/M, Z16.D, Z26.D

0x41d6dc ADD	Z29.D, Z29.D, Z9.D

0x41d6e0 ADR	Z23.D, [Z9, Z23.D,SXTW]    [3]

0x41d6e4 ADD	Z31.D, Z31.D, Z9.D

0x41d6e8 FDIVR	Z30.D, P0/M, Z30.D, Z8.D

0x41d6ec LD1D	{Z29.D}, P0/Z, [X28, Z29.D,LSL #3]    [9]

0x41d6f0 LD1D	{Z23.D}, P0/Z, [X28, Z23.D,LSL #3]    [2]

0x41d6f4 LD1D	{Z31.D}, P0/Z, [X28, Z31.D,LSL #3]    [1]

0x41d6f8 FSUB	Z9.D, Z29.D, Z23.D

0x41d6fc FSUB	Z8.D, Z31.D, Z29.D

0x41d700 FABD	Z31.D, P0/M, Z31.D, Z29.D

0x41d704 FABD	Z23.D, P0/M, Z23.D, Z29.D

0x41d708 FMUL	Z9.D, Z8.D, Z9.D

0x41d70c FCMGT	P2.D, P0/Z, Z8.D, #0

0x41d710 FCMGT	P1.D, P0/Z, Z9.D, #0

0x41d714 LD1D	{Z25.D}, P1/Z, [X26, Z25.D,SXTW #3]    [8]

0x41d718 LD1D	{Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]    [6]

0x41d71c FSUB	Z9.D, Z20.D, Z30.D

0x41d720 FMUL	Z9.D, Z31.D, Z9.D

0x41d724 MOVPRFX	Z8, Z9

0x41d728 FDIV	Z8.D, P0/M, Z8.D, Z25.D

0x41d72c MOVPRFX	Z9, Z23

0x41d730 FMLA	Z9.D, P0/M, Z30.D, Z23.D

0x41d734 FDIVR	Z28.D, P0/M, Z28.D, Z9.D

0x41d738 FMUL	Z25.D, Z25.D, Z22.D

0x41d73c FADD	Z28.D, Z28.D, Z8.D

0x41d740 FMUL	Z25.D, Z25.D, Z28.D

0x41d744 FMINNM	Z23.D, P0/M, Z23.D, Z25.D

0x41d748 FMINNM	Z23.D, P0/M, Z23.D, Z31.D

0x41d74c MOVPRFX	Z25, Z23

0x41d750 FNEG	Z25.D, P0/M, Z23.D

0x41d754 SEL	Z23.D, P2, Z23.D, Z25.D

0x41d758 MOVPRFX	Z25, Z30

0x41d75c FSUBR	Z25.D, P0/M, Z25.D, #1

0x41d760 SEL	Z23.D, P1, Z23.D, Z21.D

0x41d764 FMAD	Z23.D, P0/M, Z25.D, Z29.D

0x41d768 FMUL	Z23.D, Z23.D, Z27.D

0x41d76c ST1D	{Z23.D}, P0, [X22, Z24.D,LSL #3]    [4]

0x41d770 B.NE	41d660

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 109 - 139

--------------------------------------------------------------------------------

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.42
Bottlenecks	P6, P7,
Function	.omp_outlined..12#0x41d4c0
Source	advec_mom.cpp:109-139,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	29.50
CQA cycles if no scalar integer	29.50
CQA cycles if FP arith vectorized	29.50
CQA cycles if fully vectorized	29.13
Front-end cycles	8.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	29.50
P6 cycles	29.50
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.31
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.68
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	80.88
Vectorization ratio load	87.50
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.24
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	62.07
Vector-efficiency ratio all	97.79
Vector-efficiency ratio load	90.63
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	91.18
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.42
Bottlenecks	P6, P7,
Function	.omp_outlined..12#0x41d4c0
Source	advec_mom.cpp:109-139,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	29.50
CQA cycles if no scalar integer	29.50
CQA cycles if FP arith vectorized	29.50
CQA cycles if fully vectorized	29.13
Front-end cycles	8.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	29.50
P6 cycles	29.50
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.31
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.68
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	80.88
Vectorization ratio load	87.50
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.24
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	62.07
Vector-efficiency ratio all	97.79
Vector-efficiency ratio load	90.63
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	91.18
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..12#0x41d4c0
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:109-139
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 29.50 to 29.12 cycles (1.01x speedup).

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU loads are used in vector version.
88% of VPU addition or subtraction instructions are used in vector version.
62% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	29.50	29.50	0.50	0.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	29.50	29.50	6.00	6.00	4.00	4.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.63
Data deps.	2.00
Overall L1	29.50

Vectorization ratios

INT

all	70%
load	87%
store	100%
mul	100%
add-sub	83%
fma	100%
other	47%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	80%
load	87%
store	100%
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 29.50 cycles. At this rate:

7% of peak load performance is reached (7.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z24.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z23.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z9, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z25.D, Z4.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z5.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z28.D, Z17.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z19.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z8, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z8.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z31.D, P1, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P1, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z6.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z24.D, P0/M, Z16.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z23.D, [Z9, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z30.D, P0/M, Z30.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z9.D, Z29.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z8.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P2.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGT P1.D, P0/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z25.D}, P1/Z, [X26, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z9.D, Z20.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z8.D, P0/M, Z8.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z9.D, P0/M, Z30.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z25.D, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z25.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z23.D, P0/M, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z23.D, P0/M, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z25.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z25.D, P0/M, Z25.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z25.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41d660 <.omp_outlined..12+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..12#0x41d4c0
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:109-139
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU loads are used in vector version.
88% of VPU addition or subtraction instructions are used in vector version.
62% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	29.50	29.50	0.50	0.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	29.50	29.50	6.00	6.00	4.00	4.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.63
Data deps.	2.00
Overall L1	29.50

Vectorization ratios

INT

all	70%
load	87%
store	100%
mul	100%
add-sub	83%
fma	100%
other	47%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	80%
load	87%
store	100%
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 29.50 cycles. At this rate:

7% of peak load performance is reached (7.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z24.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z23.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z9, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z25.D, Z4.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z5.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z28.D, Z17.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z19.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z8, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z8.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z31.D, P1, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P1, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z6.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z24.D, P0/M, Z16.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z23.D, [Z9, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z30.D, P0/M, Z30.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z9.D, Z29.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z8.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P2.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGT P1.D, P0/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z25.D}, P1/Z, [X26, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z9.D, Z20.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z8.D, P0/M, Z8.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z9.D, P0/M, Z30.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z25.D, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z25.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z23.D, P0/M, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z23.D, P0/M, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z25.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z25.D, P0/M, Z25.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z25.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41d660 <.omp_outlined..12+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code