OV - exec - Loop 177

	Loop Id: 177	Module: exec	Source: field_summary.cpp:76-91 [...]	Coverage: 0.35%

0x421b60 MOVPRFX	Z29, Z0

0x421b64 SXTW	Z29.D, P0/M, Z0.D

0x421b68 SDIV	Z29.D, P0/M, Z29.D, Z21.D

0x421b6c MOVPRFX	Z30, Z0

0x421b70 MLS	Z30.D, P0/M, Z29.D, Z2.D

0x421b74 ADD	Z30.D, Z3.D, Z30.D

0x421b78 MOVPRFX	Z12, Z30

0x421b7c SXTW	Z12.D, P0/M, Z30.D

0x421b80 ADD	Z0.D, Z0.D, Z1.D

0x421b84 SUBS	W7, W7, W6

0x421b88 ADR	Z11.D, [Z24, Z30.D,SXTW #3]    [11]

0x421b8c ADD	Z29.D, Z5.D, Z29.D

0x421b90 SXTW	Z29.D, P0/M, Z29.D

0x421b94 MOVPRFX	Z31, Z6

0x421b98 MUL	Z31.D, P0/M, Z31.D, Z29.D

0x421b9c ADR	Z31.D, [Z22, Z31.D,LSL #3]    [6]

0x421ba0 MOVPRFX	Z9, Z7

0x421ba4 MUL	Z9.D, P0/M, Z9.D, Z29.D

0x421ba8 ADR	Z9.D, [Z28, Z9.D,LSL #3]    [20]

0x421bac ADR	Z8.D, [Z31, Z30.D,SXTW #3]    [10]

0x421bb0 ADR	Z10.D, [Z9, Z30.D,SXTW #3]    [16]

0x421bb4 ADD	Z9.D, Z9.D, Z11.D

0x421bb8 ADD	Z31.D, Z31.D, Z11.D

0x421bbc LD1D	{Z8.D}, P0/Z, [V8.D]    [9]

0x421bc0 LD1D	{Z10.D}, P0/Z, [V10.D]    [14]

0x421bc4 LD1D	{Z9.D}, P0/Z, [V9.D]    [3]

0x421bc8 LD1D	{Z31.D}, P0/Z, [V31.D]    [8]

0x421bcc MOVPRFX	Z13, Z29

0x421bd0 ADD	Z13.D, Z13.D, #1

0x421bd4 MOVPRFX	Z14, Z13

0x421bd8 MUL	Z14.D, P0/M, Z14.D, Z6.D

0x421bdc MUL	Z13.D, P0/M, Z13.D, Z7.D

0x421be0 ADR	Z14.D, [Z22, Z14.D,LSL #3]    [7]

0x421be4 ADR	Z15.D, [Z14, Z30.D,SXTW #3]    [2]

0x421be8 FMUL	Z8.D, Z8.D, Z8.D

0x421bec LD1D	{Z15.D}, P0/Z, [V15.D]    [4]

0x421bf0 ADR	Z13.D, [Z28, Z13.D,LSL #3]    [5]

0x421bf4 FMLA	Z8.D, P0/M, Z10.D, Z10.D

0x421bf8 ADR	Z30.D, [Z13, Z30.D,SXTW #3]    [18]

0x421bfc ADD	Z13.D, Z13.D, Z11.D

0x421c00 ADD	Z11.D, Z14.D, Z11.D

0x421c04 LD1D	{Z30.D}, P0/Z, [V30.D]    [13]

0x421c08 LD1D	{Z13.D}, P0/Z, [V13.D]    [15]

0x421c0c LD1D	{Z11.D}, P0/Z, [V11.D]    [1]

0x421c10 FMLA	Z8.D, P0/M, Z9.D, Z9.D

0x421c14 MOVPRFX	Z9, Z12

0x421c18 MLA	Z9.D, P0/M, Z18.D, Z29.D

0x421c1c FMAD	Z31.D, P0/M, Z31.D, Z8.D

0x421c20 MOVPRFX	Z8, Z12

0x421c24 MLA	Z8.D, P0/M, Z17.D, Z29.D

0x421c28 FMLA	Z31.D, P0/M, Z15.D, Z15.D

0x421c2c FMAD	Z30.D, P0/M, Z30.D, Z31.D

0x421c30 MOVPRFX	Z31, Z12

0x421c34 MLA	Z31.D, P0/M, Z16.D, Z29.D

0x421c38 MAD	Z29.D, P0/M, Z19.D, Z12.D

0x421c3c LD1D	{Z31.D}, P0/Z, [X1, Z31.D,LSL #3]    [19]

0x421c40 LD1D	{Z8.D}, P0/Z, [X2, Z8.D,LSL #3]    [12]

0x421c44 LD1D	{Z9.D}, P0/Z, [X3, Z9.D,LSL #3]    [21]

0x421c48 FMLA	Z30.D, P0/M, Z13.D, Z13.D

0x421c4c FMUL	Z8.D, Z8.D, Z31.D

0x421c50 FADD	Z4.D, Z31.D, Z4.D

0x421c54 LD1D	{Z29.D}, P0/Z, [X4, Z29.D,LSL #3]    [17]

0x421c58 FMLA	Z23.D, P0/M, Z9.D, Z8.D

0x421c5c FADD	Z20.D, Z8.D, Z20.D

0x421c60 FMLA	Z30.D, P0/M, Z11.D, Z11.D

0x421c64 FMLA	Z27.D, P0/M, Z29.D, Z31.D

0x421c68 FMUL	Z30.D, Z30.D, Z25.D

0x421c6c FMLA	Z26.D, P0/M, Z30.D, Z8.D

0x421c70 B.NE	421b60

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp: 76 - 91

--------------------------------------------------------------------------------

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.19
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4219c0
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	27.50
CQA cycles if no scalar integer	27.50
CQA cycles if FP arith vectorized	27.50
CQA cycles if fully vectorized	24.13
Front-end cycles	8.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	27.50
P6 cycles	27.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.64
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	40.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.96
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.59
Vectorization ratio load	57.14
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	58.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	23.08
Vector-efficiency ratio all	88.79
Vector-efficiency ratio load	67.86
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	68.23
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.19
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4219c0
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	27.50
CQA cycles if no scalar integer	27.50
CQA cycles if FP arith vectorized	27.50
CQA cycles if fully vectorized	24.13
Front-end cycles	8.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	27.50
P6 cycles	27.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.64
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	40.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.96
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.59
Vectorization ratio load	57.14
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	58.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	23.08
Vector-efficiency ratio all	88.79
Vector-efficiency ratio load	67.86
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	68.23
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x4219c0
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp:76-91

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.50 to 24.12 cycles (1.14x speedup).

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

57% of VPU loads are used in vector version.
58% of VPU addition or subtraction instructions are used in vector version.
23% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (40 inside FMA instructions)
52: multiply (40 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	27.50	27.50	4.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	27.50	27.50	7.50	7.50	4.00	4.00	4.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.63
Data deps.	2.00
Overall L1	27.50

Vectorization ratios

INT

all	62%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	54%
fma	100%
other	28%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	58%
fma	100%
div/sqrt	100%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.50 cycles. At this rate:

14% of peak load performance is reached (13.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SDIV Z29.D, P0/M, Z29.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z30, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z30.D, P0/M, Z29.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z30.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z12.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUBS W7, W7, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADR Z11.D, [Z24, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z29.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z31, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z31.D, [Z22, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z9, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z9.D, [Z28, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z8.D, [Z31, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z10.D, [Z9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z31.D, Z31.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z31.D}, P0/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z13.D, Z13.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z14, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MUL Z13.D, P0/M, Z13.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z14.D, [Z22, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z15.D, [Z14, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z8.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
ADR Z13.D, [Z28, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z8.D, P0/M, Z10.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
ADR Z30.D, [Z13, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z13.D, Z13.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z11.D, Z14.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
FMLA Z8.D, P0/M, Z9.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
MOVPRFX Z9, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z18.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMAD Z31.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
MOVPRFX Z8, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z17.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMLA Z31.D, P0/M, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMAD Z30.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
MOVPRFX Z31, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z16.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MAD Z29.D, P0/M, Z19.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X1, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z8.D}, P0/Z, [X2, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z9.D}, P0/Z, [X3, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMLA Z30.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMUL Z8.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z4.D, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X4, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMLA Z23.D, P0/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FADD Z20.D, Z8.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z30.D, P0/M, Z11.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMLA Z27.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMUL Z30.D, Z30.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z26.D, P0/M, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
B.NE 421b60 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x4219c0
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp:76-91

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

57% of VPU loads are used in vector version.
58% of VPU addition or subtraction instructions are used in vector version.
23% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (40 inside FMA instructions)
52: multiply (40 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	27.50	27.50	4.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	27.50	27.50	7.50	7.50	4.00	4.00	4.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.63
Data deps.	2.00
Overall L1	27.50

Vectorization ratios

INT

all	62%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	54%
fma	100%
other	28%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	58%
fma	100%
div/sqrt	100%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.50 cycles. At this rate:

14% of peak load performance is reached (13.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SDIV Z29.D, P0/M, Z29.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z30, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z30.D, P0/M, Z29.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z30.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z12.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUBS W7, W7, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADR Z11.D, [Z24, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z29.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z31, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z31.D, [Z22, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z9, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z9.D, [Z28, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z8.D, [Z31, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z10.D, [Z9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z31.D, Z31.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z31.D}, P0/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z13.D, Z13.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z14, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MUL Z13.D, P0/M, Z13.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z14.D, [Z22, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z15.D, [Z14, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z8.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
ADR Z13.D, [Z28, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z8.D, P0/M, Z10.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
ADR Z30.D, [Z13, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z13.D, Z13.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z11.D, Z14.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2
FMLA Z8.D, P0/M, Z9.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
MOVPRFX Z9, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z18.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMAD Z31.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
MOVPRFX Z8, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z17.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMLA Z31.D, P0/M, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMAD Z30.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
MOVPRFX Z31, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z16.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MAD Z29.D, P0/M, Z19.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X1, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z8.D}, P0/Z, [X2, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z9.D}, P0/Z, [X3, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMLA Z30.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMUL Z8.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z4.D, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X4, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMLA Z23.D, P0/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FADD Z20.D, Z8.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z30.D, P0/M, Z11.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMLA Z27.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMUL Z30.D, Z30.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z26.D, P0/M, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
B.NE 421b60 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code