OV - exec - Loop 167

0x423608 MOVPRFX	Z20, Z0

0x42360c SDIV	Z20.D, P0/M, Z20.D, Z2.D

0x423610 ADD	Z21.D, Z3.D, Z20.D

0x423614 MSB	Z20.D, P0/M, Z2.D, Z0.D

0x423618 ADD	Z0.D, Z0.D, Z1.D

0x42361c SUBS	X12, X12, X10

0x423620 SXTW	Z21.D, P0/M, Z21.D

0x423624 ADD	Z20.D, Z4.D, Z20.D

0x423628 SXTW	Z20.D, P0/M, Z20.D

0x42362c MOVPRFX	Z22, Z20

0x423630 MLA	Z22.D, P0/M, Z5.D, Z21.D

0x423634 LD1D	{Z23.D}, P0/Z, [X23, Z22.D,LSL #3]    [3]

0x423638 MOVPRFX	Z25, Z20

0x42363c MLA	Z25.D, P0/M, Z6.D, Z21.D

0x423640 LD1D	{Z25.D}, P0/Z, [X27, Z25.D,LSL #3]    [4]

0x423644 FMUL	Z24.D, Z23.D, Z18.D

0x423648 FDIVR	Z23.D, P0/M, Z23.D, Z17.D

0x42364c FMUL	Z24.D, Z24.D, Z25.D

0x423650 MOVPRFX	Z25, Z20

0x423654 MLA	Z25.D, P0/M, Z7.D, Z21.D

0x423658 MLA	Z20.D, P0/M, Z16.D, Z21.D

0x42365c FABS	Z23.D, P0/M, Z23.D

0x423660 ST1D	{Z24.D}, P0, [X25, Z25.D,LSL #3]    [1]

0x423664 LD1D	{Z22.D}, P0/Z, [X23, Z22.D,LSL #3]    [3]

0x423668 FMUL	Z22.D, Z19.D, Z22.D

0x42366c FMUL	Z22.D, Z24.D, Z22.D

0x423670 FSQRT	Z22.D, P0/M, Z22.D

0x423674 FMUL	Z22.D, Z22.D, Z23.D

0x423678 ST1D	{Z22.D}, P0, [X19, Z20.D,LSL #3]    [2]

0x42367c B.NE	423608

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp: 38 - 45

--------------------------------------------------------------------------------

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.07
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4234c0
Source	context.h:69-69,ideal_gas.cpp:38-45
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	3.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.43
Nb FLOP add-sub	0.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.91
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	82.76
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	87.50
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	97.41
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	90.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.07
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4234c0
Source	context.h:69-69,ideal_gas.cpp:38-45
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	3.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.43
Nb FLOP add-sub	0.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.91
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	82.76
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	87.50
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	97.41
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	90.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x4234c0
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:38-45

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

82% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU addition or subtraction instructions are used in vector version.
42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

20: multiply
4: divide
4: square root

The binary loop is loading 96 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.50	11.50	1.00	1.00	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.50	11.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	11.50

Vectorization ratios

INT

all	76%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	87%
fma	100%
other	42%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	82%
load	100%
store	100%
mul	100%
add-sub	87%
fma	100%
div/sqrt	100%
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

8% of peak load performance is reached (8.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423608

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z21.D, Z3.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z20.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z22, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z5.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z6.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z25.D}, P0/Z, [X27, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z24.D, Z23.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z23.D, P0/M, Z23.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z24.D, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z25, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z7.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MLA Z20.D, P0/M, Z16.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FABS Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P0, [X25, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z22.D}, P0/Z, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z22.D, Z19.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSQRT Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FMUL Z22.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z22.D}, P0, [X19, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 423608 <.omp_outlined.+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x4234c0
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:38-45

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

82% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU addition or subtraction instructions are used in vector version.
42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

20: multiply
4: divide
4: square root

The binary loop is loading 96 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.50	11.50	1.00	1.00	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.50	11.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	11.50

Vectorization ratios

INT

all	76%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	87%
fma	100%
other	42%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	82%
load	100%
store	100%
mul	100%
add-sub	87%
fma	100%
div/sqrt	100%
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

8% of peak load performance is reached (8.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423608

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z21.D, Z3.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z20.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z22, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z5.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z6.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z25.D}, P0/Z, [X27, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z24.D, Z23.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z23.D, P0/M, Z23.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z24.D, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z25, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z7.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MLA Z20.D, P0/M, Z16.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FABS Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P0, [X25, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z22.D}, P0/Z, [X23, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z22.D, Z19.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSQRT Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FMUL Z22.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z22.D}, P0, [X19, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 423608 <.omp_outlined.+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code