OV - exec - Function .omp_outlined..2#0x41c750

	Function: .omp_outlined..2#0x41c750	Module: exec	Source: advec_mom.cpp:53-57 [...]	Coverage: 2.66%

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 53 - 57

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41c750 SUB	SP, SP, #192

0x41c754 STP	X29, X30, [SP, #96]

0x41c758 STP	X28, X27, [SP, #112]

0x41c75c STP	X26, X25, [SP, #128]

0x41c760 STP	X24, X23, [SP, #144]

0x41c764 STP	X22, X21, [SP, #160]

0x41c768 STP	X20, X19, [SP, #176]

0x41c76c ADD	X29, SP, #96

0x41c770 LDR	W8, [X3]

0x41c774 LDR	W20, [X2]

0x41c778 LDR	W9, [X5]

0x41c77c ADD	W8, W8, #4

0x41c780 LDR	W14, [X4]

0x41c784 ADD	W9, W9, #4

0x41c788 CMP	W8, W20

0x41c78c CCMP	W9, W14, #8, #10

0x41c790 B.LT	41ca0c

0x41c794 LDP	X11, X10, [X29, #104]

0x41c798 LDR	X12, [X29, #96]

0x41c79c LDR	X13, [X6]

0x41c7a0 SUB	W23, W20, #1

0x41c7a4 SUB	X3, X29, #28

0x41c7a8 SUB	X4, X29, #8

0x41c7ac SUB	X5, X29, #16

0x41c7b0 MOVZ	W2, #34

0x41c7b4 LDR	X15, [X7]

0x41c7b8 SUB	W8, W8, W23

0x41c7bc LDR	W1, [X0]

0x41c7c0 LDR	X22, [X6, #16]

0x41c7c4 ADRP	X0,

0x41c7c8 ADD	X0, X0, #3624

0x41c7cc SUB	X6, X29, #24

0x41c7d0 LDR	X24, [X7, #16]

0x41c7d4 MOVZ	W7, #1

0x41c7d8 LDR	X19, [X10]

0x41c7dc LDR	X21, [X10, #16]

0x41c7e0 SUB	W10, W14, #1

0x41c7e4 STUR	X13, [X29, #472]

0x41c7e8 LDR	X13, [X12]

0x41c7ec LDR	X26, [X12, #16]

0x41c7f0 LDR	X12, [X11]

0x41c7f4 LDR	X28, [X11, #16]

0x41c7f8 SUB	W25, W9, W10

0x41c7fc MOVN	X9, #0

0x41c800 STR	X10, [SP, #16]

0x41c804 STP	W1, WZR, [X29, #480]

0x41c808 UMADDL	X27, W25, W8, X9

0x41c80c MOVZ	W8, #1

0x41c810 STP	X13, X15, [SP, #40]

0x41c814 STP	X14, X12, [SP, #24]

0x41c818 STUR	X8, [X29, #488]

0x41c81c STR	X8, [SP]

0x41c820 STP	X27, XZR, [X29, #1008]

0x41c824 BL	4033a0

0x41c828 LDP	X8, X13, [X29, #1008]

0x41c82c CMP	X8, X27

0x41c830 CSEL	X8, X8, X27, #11

0x41c834 CMP	X13, X8

0x41c838 B.GT	41c9fc

0x41c83c SUB	X9, X8, X13

0x41c840 CNTD	X10, ALL

0x41c844 ADD	X11, X9, #1

0x41c848 ORR	X9, XZR, X13

0x41c84c CMP	X11, X10

0x41c850 B.CC	41c95c

0x41c854 UDIV	X9, X11, X10

0x41c858 PTRUE	P0.D, ALL

0x41c85c MADD	X12, X9, X10, XZR

0x41c860 INDEX	Z0.D, X13, #1

0x41c864 ADD	X9, X13, X12

0x41c868 LDR	X13, [SP, #16]

0x41c86c DUP	Z1.D, X10

0x41c870 SUB	X11, X11, X12

0x41c874 DUP	Z2.D, X25

0x41c878 DUP	Z3.D, X23

0x41c87c DUP	Z17.D, X20

0x41c880 DUP	Z18.D, X19

0x41c884 DUP	Z4.D, X13

0x41c888 LDR	X13, [SP, #48]

0x41c88c DUP	Z5.D, X13

0x41c890 LDR	X13, [SP, #24]

0x41c894 DUP	Z6.D, X13

0x41c898 LDR	X13, [SP, #40]

0x41c89c DUP	Z7.D, X13

0x41c8a0 LDUR	X13, [X29, #472]

0x41c8a4 DUP	Z16.D, X13

0x41c8a8 LDR	X13, [SP, #32]

0x41c8ac DUP	Z19.D, X13

0x41c8b0 HINT	#0

0x41c8b4 HINT	#0

0x41c8b8 HINT	#0

0x41c8bc HINT	#0

(217) 0x41c8c0 MOVPRFX	Z20, Z0

(217) 0x41c8c4 SDIV	Z20.D, P0/M, Z20.D, Z2.D

(217) 0x41c8c8 ADD	Z21.D, Z3.D, Z20.D

(217) 0x41c8cc MOVPRFX	Z22, Z0

(217) 0x41c8d0 MLS	Z22.D, P0/M, Z20.D, Z2.D

(217) 0x41c8d4 ADD	Z23.D, Z4.D, Z22.D

(217) 0x41c8d8 MOVPRFX	Z24, Z23

(217) 0x41c8dc SXTW	Z24.D, P0/M, Z23.D

(217) 0x41c8e0 SUBS	X12, X12, X10

(217) 0x41c8e4 ADD	Z22.D, Z6.D, Z22.D

(217) 0x41c8e8 ADD	Z20.D, Z17.D, Z20.D

(217) 0x41c8ec ADD	Z0.D, Z0.D, Z1.D

(217) 0x41c8f0 SXTW	Z21.D, P0/M, Z21.D

(217) 0x41c8f4 MOVPRFX	Z26, Z7

(217) 0x41c8f8 MUL	Z26.D, P0/M, Z26.D, Z21.D

(217) 0x41c8fc MOVPRFX	Z25, Z24

(217) 0x41c900 MLA	Z25.D, P0/M, Z5.D, Z21.D

(217) 0x41c904 LD1D	{Z25.D}, P0/Z, [X24, Z25.D,LSL #3]

(217) 0x41c908 ADR	Z22.D, [Z26, Z22.D,SXTW]

(217) 0x41c90c LD1D	{Z22.D}, P0/Z, [X26, Z22.D,LSL #3]

(217) 0x41c910 ADR	Z23.D, [Z26, Z23.D,SXTW]

(217) 0x41c914 LD1D	{Z23.D}, P0/Z, [X26, Z23.D,LSL #3]

(217) 0x41c918 SXTW	Z20.D, P0/M, Z20.D

(217) 0x41c91c MAD	Z20.D, P0/M, Z18.D, Z24.D

(217) 0x41c920 FADD	Z22.D, Z22.D, Z25.D

(217) 0x41c924 FSUB	Z22.D, Z22.D, Z23.D

(217) 0x41c928 MOVPRFX	Z23, Z24

(217) 0x41c92c MLA	Z23.D, P0/M, Z16.D, Z21.D

(217) 0x41c930 ST1D	{Z22.D}, P0, [X22, Z23.D,LSL #3]

(217) 0x41c934 LD1D	{Z20.D}, P0/Z, [X21, Z20.D,LSL #3]

(217) 0x41c938 FADD	Z20.D, Z20.D, Z22.D

(217) 0x41c93c MOVPRFX	Z22, Z24

(217) 0x41c940 MLA	Z22.D, P0/M, Z18.D, Z21.D

(217) 0x41c944 LD1D	{Z22.D}, P0/Z, [X21, Z22.D,LSL #3]

(217) 0x41c948 FSUB	Z20.D, Z20.D, Z22.D

(217) 0x41c94c MAD	Z21.D, P0/M, Z19.D, Z24.D

(217) 0x41c950 ST1D	{Z20.D}, P0, [X28, Z21.D,LSL #3]

(217) 0x41c954 B.NE	41c8c0

0x41c958 CBZ	X11, 41c9fc

0x41c95c LDP	X12, X1, [SP, #24]

0x41c960 LDUR	X17, [X29, #472]

0x41c964 LDP	X0, X18, [SP, #40]

0x41c968 SUB	X10, X9, #1

0x41c96c SUB	W11, WZR, W25

0x41c970 ADD	W9, W12, W9

0x41c974 HINT	#0

0x41c978 HINT	#0

0x41c97c HINT	#0

(216) 0x41c980 ADD	X10, X10, #1

(216) 0x41c984 SDIV	X12, X10, X25

(216) 0x41c988 CMP	X8, X10

(216) 0x41c98c MADD	W14, W11, W12, W9

(216) 0x41c990 ADD	W13, W23, W12

(216) 0x41c994 ADD	W12, W20, W12

(216) 0x41c998 ADD	W9, W9, #1

(216) 0x41c99c SUB	W15, W14, #1

(216) 0x41c9a0 SBFM	X13, X13, #0, #31

(216) 0x41c9a4 SBFM	X12, X12, #0, #31

(216) 0x41c9a8 SBFM	X15, X15, #0, #31

(216) 0x41c9ac MADD	X16, X18, X13, X15

(216) 0x41c9b0 MADD	X12, X19, X12, X15

(216) 0x41c9b4 LDR	D0, [X24, X16,LSL #3]

(216) 0x41c9b8 MADD	X16, X0, X13, XZR

(216) 0x41c9bc ADD	X14, X16, W14,SXTW

(216) 0x41c9c0 LDR	D1, [X26, X14,LSL #3]

(216) 0x41c9c4 ADD	X14, X16, X15

(216) 0x41c9c8 FADD	D0, D1, D0

(216) 0x41c9cc LDR	D1, [X26, X14,LSL #3]

(216) 0x41c9d0 MADD	X14, X17, X13, X15

(216) 0x41c9d4 FSUB	D0, D0, S1

(216) 0x41c9d8 STR	D0, [X22, X14,LSL #3]

(216) 0x41c9dc LDR	D1, [X21, X12,LSL #3]

(216) 0x41c9e0 MADD	X12, X19, X13, X15

(216) 0x41c9e4 FADD	D0, D1, D0

(216) 0x41c9e8 LDR	D1, [X21, X12,LSL #3]

(216) 0x41c9ec MADD	X12, X1, X13, X15

(216) 0x41c9f0 FSUB	D0, D0, S1

(216) 0x41c9f4 STR	D0, [X28, X12,LSL #3]

(216) 0x41c9f8 B.NE	41c980

0x41c9fc LDUR	W1, [X29, #480]

0x41ca00 ADRP	X0,

0x41ca04 ADD	X0, X0, #3648

0x41ca08 BL	403260

0x41ca0c LDP	X20, X19, [SP, #176]

0x41ca10 LDP	X22, X21, [SP, #160]

0x41ca14 LDP	X24, X23, [SP, #144]

0x41ca18 LDP	X26, X25, [SP, #128]

0x41ca1c LDP	X28, X27, [SP, #112]

0x41ca20 LDP	X29, X30, [SP, #96]

0x41ca24 ADD	SP, SP, #192

0x41ca28 RET

0x41ca2c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:53-57
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 12.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 1.00 cycles (16.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 328 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	115
loop length	460
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00
cycles	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.38
Overall L1	16.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

21% of peak load performance is reached (20.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W14, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, W14, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 41ca0c <.omp_outlined..2+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <45e7c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W1, WZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMADDL X27, W25, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X13, X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41c9fc <.omp_outlined..2+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X9, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41c95c <.omp_outlined..2+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z17.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z18.D, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z16.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X11, 41c9fc <.omp_outlined..2+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X1, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X17, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X0, X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W11, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDUR W1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <45ea00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3648	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:53-57
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 1.00 cycles (16.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 328 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	115
loop length	460
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00
cycles	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.38
Overall L1	16.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

21% of peak load performance is reached (20.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W14, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, W14, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 41ca0c <.omp_outlined..2+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <45e7c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W25, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W1, WZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMADDL X27, W25, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X13, X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41c9fc <.omp_outlined..2+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X9, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41c95c <.omp_outlined..2+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z17.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z18.D, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z16.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X11, 41c9fc <.omp_outlined..2+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X1, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X17, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X0, X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W11, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDUR W1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <45ea00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3648	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..2#0x41c750–	2.66	3.54
○Loop 217 - advec_mom.cpp:54-57 - exec	2.66	3.52
○Loop 216 - advec_mom.cpp:54-57 - exec	0	0

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ASM code

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Vectorization

Details

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Matching between your function (in the source code) and the binary function

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Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code