OV - exec - Loop 653

	Loop Id: 653	Module: exec	Source: update_halo.cpp:580-583	Coverage: 0.02%

0x4318e0 ORR	W1, WZR, W19

0x4318e4 ADRP	X0,

0x4318e8 ADD	X0, X0, #2216

0x4318ec BL	403260

0x4318f0 LDP	X20, X19, [SP, #112]

0x4318f4 LDP	X22, X21, [SP, #96]

0x4318f8 LDP	X24, X23, [SP, #80]

0x4318fc LDP	X26, X25, [SP, #64]

0x431900 LDP	X28, X27, [SP, #48]

0x431904 LDP	X29, X30, [SP, #32]

0x431908 ADD	SP, SP, #128

0x43190c RET

0x431910 ADD	X15, X21, #24

0x431914 UBFM	X16, X20, #61, #60

0x431918 ADD	W14, W9, W22

0x43191c ADD	X6, X21, #16

0x431920 MOVZ	W0, #12

0x431924 RDVL	X5, #1

0x431928 SUB	X11, X20, #1

0x43192c ORR	W10, WZR, WZR

0x431930 RDVL	X18, #2

0x431934 RDVL	X1, #62

0x431938 ADD	X2, X15, X16

0x43193c ADD	X12, X21, #8

0x431940 UBFM	X13, X23, #61, #60

0x431944 SUB	X16, X21, X16

0x431948 SUB	X17, XZR, X11,LSL #3

0x43194c ADD	X3, X16, #16

0x431950 CNTW	X16, ALL

0x431954 CMP	X16, #12

0x431958 SUB	W14, W14, W20

0x43195c ADD	W14, W14, #1

0x431960 ADDVL	X4, X15, #1

0x431964 SUB	X5, X6, X5

0x431968 CSEL	X0, X16, X0, #8

0x43196c CMP	X15, X6

0x431970 ADDVL	X6, X6, #62

0x431974 CCMP	X3, X2, #2, #3

0x431978 PTRUE	P0.B, ALL

0x43197c PTRUE	P1.D, ALL

0x431980 ADD	X3, X21, #48

0x431984 CSINC	W2, WZR, WZR, #2

0x431988 ORR	W7, WZR, W14

0x43198c B	4319b4

0x4319a0 CMP	W9, W8

0x4319a4 ADD	W9, W9, #1

0x4319a8 ADD	W10, W10, #1

0x4319ac ADD	W7, W7, #1

0x4319b0 B.EQ	4318e0

0x4319b4 SBFM	X22, X7, #0, #31

0x4319b8 CMP	X0, X20

0x4319bc MADD	X22, X13, X22, XZR

0x4319c0 B.HI	4319e4

0x4319c4 ADD	W23, W14, W10

0x4319c8 ANDS	XZR, X11, #4227

0x4319cc SBFM	X23, X23, #0, #31

0x4319d0 MADD	X23, X13, X23, X12

0x4319d4 ADD	X24, X23, X17

0x4319d8 CCMP	X24, X23, #2, #0

0x4319dc CSINC	W23, W2, WZR, #9

0x4319e0 TBZ	W23, #0, 431a88

0x4319e4 ORR	X23, XZR, XZR

0x4319e8 SUB	W24, W20, W23

0x4319ec ANDS	X25, X24, #4160

0x4319f0 ORR	X24, XZR, X23

0x4319f4 B.EQ	431a20

0x4319f8 SUB	X24, X22, X23,LSL #3

0x4319fc ADD	X26, X15, X22

0x431a00 ADD	X27, X12, X24

0x431a04 ORR	X24, XZR, X23

  (655) 0x431a08 LDR	D0, [X26, X24,LSL #3]

  (655) 0x431a0c ADD	X24, X24, #1

  (655) 0x431a10 SUBS	X25, X25, #1

  (655) 0x431a14 FNEG	D0, D0

  (655) 0x431a18 STR	D0, [X27], #504

  (655) 0x431a1c B.NE	431a08

0x431a20 ORN	X23, XZR, X23

0x431a24 ADD	X23, X23, X20

0x431a28 CMP	X23, #3

0x431a2c B.CC	4319a0

0x431a30 UBFM	X25, X24, #61, #60

0x431a34 SUB	X24, X20, X24

0x431a38 ADD	X23, X22, X25

0x431a3c SUB	X22, X22, X25

0x431a40 ADD	X23, X3, X23

0x431a44 ADD	X22, X21, X22

  (654) 0x431a48 LDUR	D0, [X23, #488]

  (654) 0x431a4c SUBS	X24, X24, #4

  (654) 0x431a50 FNEG	D0, D0

  (654) 0x431a54 STR	D0, [X22, #8]

  (654) 0x431a58 LDUR	D0, [X23, #496]

  (654) 0x431a5c FNEG	D0, D0

  (654) 0x431a60 STR	D0, [X22]

  (654) 0x431a64 LDUR	D0, [X23, #504]

  (654) 0x431a68 FNEG	D0, D0

  (654) 0x431a6c STUR	D0, [X22, #504]

  (654) 0x431a70 LDR	D0, [X23], #32

  (654) 0x431a74 FNEG	D0, D0

  (654) 0x431a78 STUR	D0, [X22, #496]

  (654) 0x431a7c SUB	X22, X22, #32

  (654) 0x431a80 B.NE	431a48

0x431a84 B	4319a0

0x431a88 UDIV	X23, X20, X16

0x431a8c ORR	X26, XZR, X6

0x431a90 ORR	X27, XZR, X5

0x431a94 ORR	X28, XZR, X4

0x431a98 ORR	X30, XZR, X15

0x431a9c UMSUBL	X24, W23, W16, X20

0x431aa0 UMADDL	X23, W23, W16, XZR

0x431aa4 ORR	X25, XZR, X23

  (656) 0x431aa8 LD1B	{Z0.B}, P0/Z, [X30, X22]

  (656) 0x431aac LD1B	{Z1.B}, P0/Z, [X28, X22]

  (656) 0x431ab0 ADD	X30, X30, X18

  (656) 0x431ab4 ADD	X28, X28, X18

  (656) 0x431ab8 SUBS	X25, X25, X16

  (656) 0x431abc FNEG	Z0.D, P1/M, Z0.D

  (656) 0x431ac0 FNEG	Z1.D, P1/M, Z1.D

  (656) 0x431ac4 REV	Z0.D, Z0.D

  (656) 0x431ac8 ST1B	{Z0.B}, P0, [X27, X22]

  (656) 0x431acc REV	Z0.D, Z1.D

  (656) 0x431ad0 ADD	X27, X27, X1

  (656) 0x431ad4 ST1B	{Z0.B}, P0, [X26, X22]

  (656) 0x431ad8 ADD	X26, X26, X1

  (656) 0x431adc B.NE	431aa8

0x431ae0 CBNZ	X24, 4319e8

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 580 - 583

--------------------------------------------------------------------------------

580: #pragma omp parallel for simd

581:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

582:         for (int j = 0; j < depth; ++j) {

583:           field.mass_flux_x(1 - j, k) = -field.mass_flux_x(1 + 2 + j, k);

Path /

Metric	Value
CQA speedup if no scalar integer	6.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..100
Source	update_halo.cpp:580-582
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.75
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	18.75
CQA cycles if fully vectorized	7.88
Front-end cycles	11.25
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	18.75
P2 cycles	18.75
P3 cycles	18.75
P4 cycles	18.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	90.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.79
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.67
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	28.50

Metric	Value
CQA speedup if no scalar integer	6.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..100
Source	update_halo.cpp:580-582
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.75
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	18.75
CQA cycles if fully vectorized	7.88
Front-end cycles	11.25
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	18.75
P2 cycles	18.75
P3 cycles	18.75
P4 cycles	18.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	90.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.79
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.67
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	28.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..100
Source file and lines	update_halo.cpp:580-583
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:580-583.

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:580-582.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.75 to 3.00 cycles (6.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 18.75 to 7.87 cycles (2.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.75 to 0.50 cycles (37.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	5.00	5.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.25
Overall L1	18.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.75 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4319a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADRP X0, <4648e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X0, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X15, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X16, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W14, W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X21, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ W0, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
RDVL X5, #1	1	0	0	0	0	1	0	0	0	0	2	1
SUB X11, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
RDVL X18, #2	1	0	0	0	0	1	0	0	0	0	2	1
RDVL X1, #62	1	0	0	0	0	1	0	0	0	0	2	1
ADD X2, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X12, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X13, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X16, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X17, XZR, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CNTW X16, ALL	1	0	0	0	0	1	0	0	0	0	2	1
CMP X16, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
SUB W14, W14, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADDVL X4, X15, #1	1	0	0	0	0	1	0	0	0	0	2	1
SUB X5, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CSEL X0, X16, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X15, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADDVL X6, X6, #62	1	0	0	0	0	1	0	0	0	0	2	1
CCMP X3, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	2	1
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	2	1
ADD X3, X21, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CSINC W2, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 4319b4 <.omp_outlined..100+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.EQ 4318e0 <.omp_outlined..100+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X22, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X0, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
MADD X22, X13, X22, XZR	1	0	0	0	0	1	0	0	0	0	2	1
B.HI 4319e4 <.omp_outlined..100+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD W23, W14, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ANDS XZR, X11, #4227	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X23, X13, X23, X12	1	0	0	0	0	1	0	0	0	0	2	1
ADD X24, X23, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CCMP X24, X23, #2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CSINC W23, W2, WZR, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
TBZ W23, #0, 431a88 <.omp_outlined..100+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W24, W20, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ANDS X25, X24, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ORR X24, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.EQ 431a20 <.omp_outlined..100+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB X24, X22, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X26, X15, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X27, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X24, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORN X23, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X23, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X23, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 4319a0 <.omp_outlined..100+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UBFM X25, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X24, X20, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X22, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X22, X22, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X3, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X21, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 4319a0 <.omp_outlined..100+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV X23, X20, X16	1	0	0	0	0	1	0	0	0	0	5-20	1-0.50
ORR X26, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X27, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X28, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X30, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UMSUBL X24, W23, W16, X20	1	0	0	0	0	1	0	0	0	0	2	1
UMADDL X23, W23, W16, XZR	1	0	0	0	0	1	0	0	0	0	2	1
ORR X25, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CBNZ X24, 4319e8 <.omp_outlined..100+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..100
Source file and lines	update_halo.cpp:580-583
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.75 to 3.00 cycles (6.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.75 to 0.50 cycles (37.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	5.00	5.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.25
Overall L1	18.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.75 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4319a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADRP X0, <4648e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X0, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X15, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X16, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W14, W9, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X21, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ W0, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
RDVL X5, #1	1	0	0	0	0	1	0	0	0	0	2	1
SUB X11, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
RDVL X18, #2	1	0	0	0	0	1	0	0	0	0	2	1
RDVL X1, #62	1	0	0	0	0	1	0	0	0	0	2	1
ADD X2, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X12, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X13, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X16, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X17, XZR, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CNTW X16, ALL	1	0	0	0	0	1	0	0	0	0	2	1
CMP X16, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
SUB W14, W14, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADDVL X4, X15, #1	1	0	0	0	0	1	0	0	0	0	2	1
SUB X5, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CSEL X0, X16, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X15, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADDVL X6, X6, #62	1	0	0	0	0	1	0	0	0	0	2	1
CCMP X3, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	2	1
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	2	1
ADD X3, X21, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CSINC W2, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 4319b4 <.omp_outlined..100+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.EQ 4318e0 <.omp_outlined..100+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X22, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X0, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
MADD X22, X13, X22, XZR	1	0	0	0	0	1	0	0	0	0	2	1
B.HI 4319e4 <.omp_outlined..100+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD W23, W14, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ANDS XZR, X11, #4227	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X23, X13, X23, X12	1	0	0	0	0	1	0	0	0	0	2	1
ADD X24, X23, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CCMP X24, X23, #2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CSINC W23, W2, WZR, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
TBZ W23, #0, 431a88 <.omp_outlined..100+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W24, W20, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ANDS X25, X24, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ORR X24, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.EQ 431a20 <.omp_outlined..100+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB X24, X22, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X26, X15, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X27, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X24, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORN X23, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X23, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X23, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 4319a0 <.omp_outlined..100+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UBFM X25, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X24, X20, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X22, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X22, X22, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X3, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X21, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 4319a0 <.omp_outlined..100+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV X23, X20, X16	1	0	0	0	0	1	0	0	0	0	5-20	1-0.50
ORR X26, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X27, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X28, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X30, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UMSUBL X24, W23, W16, X20	1	0	0	0	0	1	0	0	0	0	2	1
UMADDL X23, W23, W16, XZR	1	0	0	0	0	1	0	0	0	0	2	1
ORR X25, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CBNZ X24, 4319e8 <.omp_outlined..100+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code