OV - exec - Loop 369

	Loop Id: 369	Module: exec	Source: advec_mom.cpp:219-221 [...]	Coverage: 3.42%

0x41e5c0 MOVPRFX	Z18, Z0

0x41e5c4 SDIV	Z18.D, P0/M, Z18.D, Z2.D

0x41e5c8 ADD	Z19.D, Z3.D, Z18.D

0x41e5cc MOVPRFX	Z20, Z0

0x41e5d0 MLS	Z20.D, P0/M, Z18.D, Z2.D

0x41e5d4 ADD	Z20.D, Z4.D, Z20.D

0x41e5d8 SUBS	X12, X12, X10

0x41e5dc ADD	Z18.D, Z7.D, Z18.D

0x41e5e0 ADD	Z0.D, Z0.D, Z1.D

0x41e5e4 SXTW	Z20.D, P0/M, Z20.D

0x41e5e8 SXTW	Z18.D, P0/M, Z18.D

0x41e5ec SXTW	Z19.D, P0/M, Z19.D

0x41e5f0 MOVPRFX	Z21, Z20

0x41e5f4 MLA	Z21.D, P0/M, Z5.D, Z19.D

0x41e5f8 LD1D	{Z22.D}, P0/Z, [X24, Z21.D,LSL #3]    [3]

0x41e5fc MOVPRFX	Z23, Z20

0x41e600 MLA	Z23.D, P0/M, Z6.D, Z19.D

0x41e604 LD1D	{Z23.D}, P0/Z, [X26, Z23.D,LSL #3]    [1]

0x41e608 MAD	Z18.D, P0/M, Z16.D, Z20.D

0x41e60c LD1D	{Z18.D}, P0/Z, [X28, Z18.D,LSL #3]    [4]

0x41e610 FMLA	Z18.D, P0/M, Z23.D, Z22.D

0x41e614 MOVPRFX	Z22, Z20

0x41e618 MLA	Z22.D, P0/M, Z16.D, Z19.D

0x41e61c LD1D	{Z22.D}, P0/Z, [X28, Z22.D,LSL #3]    [2]

0x41e620 MAD	Z19.D, P0/M, Z17.D, Z20.D

0x41e624 FSUB	Z18.D, Z18.D, Z22.D

0x41e628 LD1D	{Z19.D}, P0/Z, [X23, Z19.D,LSL #3]    [5]

0x41e62c FDIV	Z18.D, P0/M, Z18.D, Z19.D

0x41e630 ST1D	{Z18.D}, P0, [X24, Z21.D,LSL #3]    [3]

0x41e634 B.NE	41e5c0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 219 - 221

--------------------------------------------------------------------------------

219:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

220:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

221:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i + 0, j - 1) - mom_flux(i, j)) / node_mass_post(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.93
Bottlenecks	P6, P7,
Function	.omp_outlined..22
Source	context.h:69-69,advec_mom.cpp:219-221
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	3.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.00
P6 cycles	11.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.45
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.31
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	90.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	37.50
Vector-efficiency ratio all	97.41
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	92.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.93
Bottlenecks	P6, P7,
Function	.omp_outlined..22
Source	context.h:69-69,advec_mom.cpp:219-221
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	3.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.00
P6 cycles	11.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.45
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.31
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	90.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	37.50
Vector-efficiency ratio all	97.41
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	92.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..22
Source file and lines	advec_mom.cpp:219-221
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:219-221

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU addition or subtraction instructions are used in vector version.
37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)
4: divide

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	0.50	0.50	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	1.00	1.00	3.00	3.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

INT

all	76%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	100%
other	44%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	79%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
div/sqrt	100%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

15% of peak load performance is reached (14.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e5c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z20.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z21.D, P0/M, Z5.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z22.D}, P0/Z, [X24, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z23, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z18.D, P0/M, Z16.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z18.D}, P0/Z, [X28, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z18.D, P0/M, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z22, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z22.D}, P0/Z, [X28, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z18.D, Z18.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X23, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z18.D, P0/M, Z18.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z18.D}, P0, [X24, Z21.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41e5c0 <.omp_outlined..22+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..22
Source file and lines	advec_mom.cpp:219-221
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:219-221

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU addition or subtraction instructions are used in vector version.
37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)
4: divide

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	0.50	0.50	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	1.00	1.00	3.00	3.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

INT

all	76%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	100%
other	44%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	79%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
div/sqrt	100%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

15% of peak load performance is reached (14.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e5c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z20.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z21.D, P0/M, Z5.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z22.D}, P0/Z, [X24, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z23, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z18.D, P0/M, Z16.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z18.D}, P0/Z, [X28, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z18.D, P0/M, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z22, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z22.D}, P0/Z, [X28, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z18.D, Z18.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X23, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z18.D, P0/M, Z18.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z18.D}, P0, [X24, Z21.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41e5c0 <.omp_outlined..22+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code