OV - exec - Loop 358

	Loop Id: 358	Module: exec	Source: advec_mom.cpp:181-211 [...]	Coverage: 7.39%

0x41e244 MOVPRFX	Z23, Z0

0x41e248 SDIV	Z23.D, P0/M, Z23.D, Z2.D

0x41e24c MOVPRFX	Z25, Z0

0x41e250 MLS	Z25.D, P0/M, Z23.D, Z2.D

0x41e254 ADD	Z25.D, Z4.D, Z25.D

0x41e258 ADD	Z24.D, Z3.D, Z23.D

0x41e25c MOVPRFX	Z26, Z24

0x41e260 SXTW	Z26.D, P0/M, Z24.D

0x41e264 SUBS	X12, X12, X10

0x41e268 ADD	Z28.D, Z17.D, Z23.D

0x41e26c MOVPRFX	Z29, Z28

0x41e270 SXTW	Z29.D, P0/M, Z28.D

0x41e274 ADD	Z30.D, Z18.D, Z23.D

0x41e278 ADD	Z23.D, Z19.D, Z23.D

0x41e27c ADD	Z0.D, Z0.D, Z1.D

0x41e280 SXTW	Z25.D, P0/M, Z25.D

0x41e284 MOVPRFX	Z27, Z25

0x41e288 MLA	Z27.D, P0/M, Z5.D, Z26.D

0x41e28c LD1D	{Z27.D}, P0/Z, [X23, Z27.D,LSL #3]    [7]

0x41e290 MOVPRFX	Z8, Z27

0x41e294 FABS	Z8.D, P0/M, Z27.D

0x41e298 FCMLT	P1.D, P0/Z, Z27.D, #0

0x41e29c SEL	Z23.D, P1, Z23.D, Z30.D

0x41e2a0 SEL	Z31.D, P1, Z26.D, Z29.D

0x41e2a4 SEL	Z29.D, P1, Z29.D, Z26.D

0x41e2a8 SEL	Z28.D, P1, Z28.D, Z30.D

0x41e2ac MOVPRFX	Z30, Z25

0x41e2b0 MLA	Z30.D, P0/M, Z29.D, Z6.D

0x41e2b4 LD1D	{Z30.D}, P0/Z, [X25, Z30.D,LSL #3]    [5]

0x41e2b8 SXTW	Z23.D, P0/M, Z23.D

0x41e2bc MAD	Z29.D, P0/M, Z7.D, Z25.D

0x41e2c0 MAD	Z31.D, P0/M, Z7.D, Z25.D

0x41e2c4 MAD	Z23.D, P0/M, Z7.D, Z25.D

0x41e2c8 FDIVR	Z30.D, P0/M, Z30.D, Z8.D

0x41e2cc LD1D	{Z29.D}, P0/Z, [X28, Z29.D,LSL #3]    [3]

0x41e2d0 LD1D	{Z23.D}, P0/Z, [X28, Z23.D,LSL #3]    [2]

0x41e2d4 LD1D	{Z31.D}, P0/Z, [X28, Z31.D,LSL #3]    [1]

0x41e2d8 FSUB	Z9.D, Z29.D, Z23.D

0x41e2dc FSUB	Z8.D, Z31.D, Z29.D

0x41e2e0 FABD	Z31.D, P0/M, Z31.D, Z29.D

0x41e2e4 FABD	Z23.D, P0/M, Z23.D, Z29.D

0x41e2e8 FMUL	Z9.D, Z8.D, Z9.D

0x41e2ec FCMGT	P2.D, P0/Z, Z8.D, #0

0x41e2f0 FCMGT	P1.D, P0/Z, Z9.D, #0

0x41e2f4 FSUB	Z9.D, Z20.D, Z30.D

0x41e2f8 LD1D	{Z24.D}, P1/Z, [X26, Z24.D,SXTW #3]    [4]

0x41e2fc LD1D	{Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]    [6]

0x41e300 FMUL	Z9.D, Z31.D, Z9.D

0x41e304 MOVPRFX	Z8, Z9

0x41e308 FDIV	Z8.D, P0/M, Z8.D, Z24.D

0x41e30c MOVPRFX	Z9, Z23

0x41e310 FMLA	Z9.D, P0/M, Z30.D, Z23.D

0x41e314 FDIVR	Z28.D, P0/M, Z28.D, Z9.D

0x41e318 FMUL	Z24.D, Z24.D, Z22.D

0x41e31c FADD	Z28.D, Z28.D, Z8.D

0x41e320 FMUL	Z24.D, Z24.D, Z28.D

0x41e324 FMINNM	Z23.D, P0/M, Z23.D, Z24.D

0x41e328 FMINNM	Z23.D, P0/M, Z23.D, Z31.D

0x41e32c MOVPRFX	Z24, Z23

0x41e330 FNEG	Z24.D, P0/M, Z23.D

0x41e334 SEL	Z23.D, P2, Z23.D, Z24.D

0x41e338 MOVPRFX	Z24, Z30

0x41e33c FSUBR	Z24.D, P0/M, Z24.D, #1

0x41e340 SEL	Z23.D, P1, Z23.D, Z21.D

0x41e344 FMAD	Z23.D, P0/M, Z24.D, Z29.D

0x41e348 MOVPRFX	Z24, Z25

0x41e34c MLA	Z24.D, P0/M, Z16.D, Z26.D

0x41e350 FMUL	Z23.D, Z23.D, Z27.D

0x41e354 ST1D	{Z23.D}, P0, [X22, Z24.D,LSL #3]    [8]

0x41e358 B.NE	41e244

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 181 - 211

--------------------------------------------------------------------------------

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.43
Bottlenecks	P6, P7,
Function	.omp_outlined..20
Source	context.h:69-69,advec_mom.cpp:181-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.00
CQA cycles if no scalar integer	30.00
CQA cycles if FP arith vectorized	30.00
CQA cycles if fully vectorized	30.00
Front-end cycles	8.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	30.00
P6 cycles	30.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	70.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.27
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.53
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	81.16
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	93.75
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	61.29
Vector-efficiency ratio all	98.91
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.31
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.43
Bottlenecks	P6, P7,
Function	.omp_outlined..20
Source	context.h:69-69,advec_mom.cpp:181-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.00
CQA cycles if no scalar integer	30.00
CQA cycles if FP arith vectorized	30.00
CQA cycles if fully vectorized	30.00
Front-end cycles	8.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	30.00
P6 cycles	30.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	70.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.27
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.53
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	81.16
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	93.75
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	61.29
Vector-efficiency ratio all	98.91
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.31
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..20
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:181-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

93% of VPU addition or subtraction instructions are used in vector version.
61% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	70
loop length	280
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	30.00	30.00	0.50	0.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	30.00	30.00	6.00	6.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.75
Data deps.	2.00
Overall L1	30.00

Vectorization ratios

INT

all	71%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
other	47%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	93%
fma	100%
div/sqrt	100%
other	61%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.00 cycles. At this rate:

7% of peak load performance is reached (7.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.07 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e244

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z25, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z25.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z25.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z24.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z28.D, Z17.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z30.D, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z19.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z5.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z8, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z8.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z23.D, P1, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P1, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z29.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z29.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z31.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z23.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FDIVR Z30.D, P0/M, Z30.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z9.D, Z29.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z8.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P2.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGT P1.D, P0/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FSUB Z9.D, Z20.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P1/Z, [X26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z9.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z8.D, P0/M, Z8.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z9.D, P0/M, Z30.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z24.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z23.D, P0/M, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z24.D, P0/M, Z24.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z24, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z16.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41e244 <.omp_outlined..20+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..20
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:181-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

93% of VPU addition or subtraction instructions are used in vector version.
61% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	70
loop length	280
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	30.00	30.00	0.50	0.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	30.00	30.00	6.00	6.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.75
Data deps.	2.00
Overall L1	30.00

Vectorization ratios

INT

all	71%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
other	47%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	93%
fma	100%
div/sqrt	100%
other	61%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.00 cycles. At this rate:

7% of peak load performance is reached (7.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.07 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e244

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z25, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z25.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z25.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z24.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z28.D, Z17.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z30.D, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z19.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z5.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z8, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z8.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z23.D, P1, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P1, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z29.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z29.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z31.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z23.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FDIVR Z30.D, P0/M, Z30.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z9.D, Z29.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z8.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P2.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGT P1.D, P0/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FSUB Z9.D, Z20.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P1/Z, [X26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z9.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z8.D, P0/M, Z8.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z9.D, P0/M, Z30.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z24.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z23.D, P0/M, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z24.D, P0/M, Z24.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z24, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z16.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41e244 <.omp_outlined..20+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code