OV - exec - Loop 347

	Loop Id: 347	Module: exec	Source: advec_mom.cpp:168-172 [...]	Coverage: 2.77%

0x41dec8 MOVPRFX	Z21, Z0

0x41decc SDIV	Z21.D, P0/M, Z21.D, Z2.D

0x41ded0 ADD	Z22.D, Z3.D, Z21.D

0x41ded4 MOVPRFX	Z23, Z0

0x41ded8 MLS	Z23.D, P0/M, Z21.D, Z2.D

0x41dedc ADD	Z24.D, Z4.D, Z23.D

0x41dee0 SUBS	X12, X12, X10

0x41dee4 ADD	Z21.D, Z20.D, Z21.D

0x41dee8 ADD	Z23.D, Z7.D, Z23.D

0x41deec ADD	Z0.D, Z0.D, Z1.D

0x41def0 SXTW	Z21.D, P0/M, Z21.D

0x41def4 MOVPRFX	Z25, Z5

0x41def8 MUL	Z25.D, P0/M, Z25.D, Z21.D

0x41defc MOVPRFX	Z27, Z6

0x41df00 MUL	Z27.D, P0/M, Z27.D, Z21.D

0x41df04 ADR	Z26.D, [Z25, Z24.D,SXTW]    [3]

0x41df08 LD1D	{Z26.D}, P0/Z, [X25, Z26.D,LSL #3]    [8]

0x41df0c ADR	Z28.D, [Z27, Z24.D,SXTW]    [19]

0x41df10 LD1D	{Z28.D}, P0/Z, [X27, Z28.D,LSL #3]    [15]

0x41df14 SXTW	Z22.D, P0/M, Z22.D

0x41df18 MOVPRFX	Z29, Z5

0x41df1c MUL	Z29.D, P0/M, Z29.D, Z22.D

0x41df20 ADR	Z30.D, [Z29, Z24.D,SXTW]    [14]

0x41df24 MOVPRFX	Z31, Z6

0x41df28 MUL	Z31.D, P0/M, Z31.D, Z22.D

0x41df2c LD1D	{Z30.D}, P0/Z, [X25, Z30.D,LSL #3]    [17]

0x41df30 ADR	Z25.D, [Z25, Z23.D,SXTW]    [18]

0x41df34 ADR	Z27.D, [Z27, Z23.D,SXTW]    [10]

0x41df38 FMUL	Z26.D, Z28.D, Z26.D

0x41df3c ADR	Z28.D, [Z31, Z24.D,SXTW]    [12]

0x41df40 SXTW	Z24.D, P0/M, Z24.D

0x41df44 LD1D	{Z28.D}, P0/Z, [X27, Z28.D,LSL #3]    [13]

0x41df48 LD1D	{Z25.D}, P0/Z, [X25, Z25.D,LSL #3]    [9]

0x41df4c LD1D	{Z27.D}, P0/Z, [X27, Z27.D,LSL #3]    [20]

0x41df50 MAD	Z21.D, P0/M, Z17.D, Z24.D

0x41df54 FMLA	Z26.D, P0/M, Z28.D, Z30.D

0x41df58 FMAD	Z25.D, P0/M, Z27.D, Z26.D

0x41df5c ADR	Z26.D, [Z29, Z23.D,SXTW]    [1]

0x41df60 ADR	Z23.D, [Z31, Z23.D,SXTW]    [7]

0x41df64 LD1D	{Z26.D}, P0/Z, [X25, Z26.D,LSL #3]    [4]

0x41df68 LD1D	{Z23.D}, P0/Z, [X27, Z23.D,LSL #3]    [2]

0x41df6c FMAD	Z23.D, P0/M, Z26.D, Z25.D

0x41df70 MOVPRFX	Z25, Z24

0x41df74 MLA	Z25.D, P0/M, Z16.D, Z22.D

0x41df78 FMUL	Z23.D, Z23.D, Z19.D

0x41df7c ST1D	{Z23.D}, P0, [X23, Z25.D,LSL #3]    [16]

0x41df80 LD1D	{Z21.D}, P0/Z, [X28, Z21.D,LSL #3]    [5]

0x41df84 FSUB	Z21.D, Z23.D, Z21.D

0x41df88 MOVPRFX	Z23, Z24

0x41df8c MLA	Z23.D, P0/M, Z17.D, Z22.D

0x41df90 LD1D	{Z23.D}, P0/Z, [X28, Z23.D,LSL #3]    [11]

0x41df94 MAD	Z22.D, P0/M, Z18.D, Z24.D

0x41df98 FADD	Z21.D, Z21.D, Z23.D

0x41df9c ST1D	{Z21.D}, P0, [X19, Z22.D,LSL #3]    [6]

0x41dfa0 B.NE	41dec8

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 168 - 172

--------------------------------------------------------------------------------

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.98
Bottlenecks	P6, P7,
Function	.omp_outlined..18
Source	context.h:69-69,advec_mom.cpp:168-172
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	20.50
CQA cycles if no scalar integer	20.50
CQA cycles if FP arith vectorized	20.50
CQA cycles if fully vectorized	17.50
Front-end cycles	6.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	20.50
P6 cycles	20.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.95
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.73
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	68.52
Vectorization ratio load	55.56
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.63
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	27.27
Vector-efficiency ratio all	87.50
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	64.47
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.98
Bottlenecks	P6, P7,
Function	.omp_outlined..18
Source	context.h:69-69,advec_mom.cpp:168-172
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	20.50
CQA cycles if no scalar integer	20.50
CQA cycles if FP arith vectorized	20.50
CQA cycles if fully vectorized	17.50
Front-end cycles	6.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	20.50
P6 cycles	20.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.95
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.73
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	68.52
Vectorization ratio load	55.56
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.63
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	27.27
Vector-efficiency ratio all	87.50
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	64.47
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..18
Source file and lines	advec_mom.cpp:168-172
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:168-172

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 20.50 to 17.50 cycles (1.17x speedup).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

55% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
27% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	20.50	20.50	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	20.50	20.50	3.50	3.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.88
Data deps.	2.00
Overall L1	20.50

Vectorization ratios

INT

all	63%
load	55%
store	100%
mul	100%
add-sub	47%
fma	100%
other	33%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	55%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.50 cycles. At this rate:

16% of peak load performance is reached (15.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dec8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z21.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z22.D, Z3.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z23.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z24.D, Z4.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z21.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z7.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z25, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z25.D, P0/M, Z25.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z27, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z27.D, P0/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z26.D, [Z25, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z28.D, [Z27, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z29, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z29.D, P0/M, Z29.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z30.D, [Z29, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z25.D, [Z25, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z27.D, [Z27, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADR Z28.D, [Z31, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P0/Z, [X25, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X27, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z21.D, P0/M, Z17.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMLA Z26.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z25.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADR Z26.D, [Z29, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z23.D, [Z31, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X27, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z23.D, P0/M, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z16.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z23.D, Z23.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X23, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P0/Z, [X28, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z17.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z22.D, P0/M, Z18.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z21.D}, P0, [X19, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41dec8 <.omp_outlined..18+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..18
Source file and lines	advec_mom.cpp:168-172
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:168-172

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

55% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
27% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	20.50	20.50	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	20.50	20.50	3.50	3.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.88
Data deps.	2.00
Overall L1	20.50

Vectorization ratios

INT

all	63%
load	55%
store	100%
mul	100%
add-sub	47%
fma	100%
other	33%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	55%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.50 cycles. At this rate:

16% of peak load performance is reached (15.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dec8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z21.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z22.D, Z3.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z23.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z24.D, Z4.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z21.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z7.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z25, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z25.D, P0/M, Z25.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z27, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z27.D, P0/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z26.D, [Z25, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z28.D, [Z27, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z29, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z29.D, P0/M, Z29.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z30.D, [Z29, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z25.D, [Z25, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z27.D, [Z27, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADR Z28.D, [Z31, Z24.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P0/Z, [X25, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X27, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z21.D, P0/M, Z17.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMLA Z26.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z25.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADR Z26.D, [Z29, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z23.D, [Z31, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X27, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z23.D, P0/M, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z16.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z23.D, Z23.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X23, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P0/Z, [X28, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z17.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z22.D, P0/M, Z18.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z21.D}, P0, [X19, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41dec8 <.omp_outlined..18+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code