OV - exec - Loop 312

	Loop Id: 312	Module: exec	Source: advec_cell.cpp:158-202 [...]	Coverage: 5.41%

0x41ba48 MOVPRFX	Z28, Z0

0x41ba4c SDIV	Z28.D, P0/M, Z28.D, Z2.D

0x41ba50 MOVPRFX	Z26, Z0

0x41ba54 MLS	Z26.D, P0/M, Z28.D, Z2.D

0x41ba58 ADD	Z26.D, Z4.D, Z26.D

0x41ba5c ADD	Z29.D, Z3.D, Z28.D

0x41ba60 MOVPRFX	Z27, Z29

0x41ba64 SXTW	Z27.D, P0/M, Z29.D

0x41ba68 SUBS	X13, X13, X11

0x41ba6c ADD	Z31.D, Z20.D, Z28.D

0x41ba70 ADD	Z8.D, Z6.D, Z28.D

0x41ba74 ADD	Z28.D, Z21.D, Z28.D

0x41ba78 FDUP	Z23.D, #0

0x41ba7c ADD	Z0.D, Z0.D, Z1.D

0x41ba80 SXTW	Z26.D, P0/M, Z26.D

0x41ba84 MOVPRFX	Z30, Z26

0x41ba88 MLA	Z30.D, P0/M, Z5.D, Z27.D

0x41ba8c LD1D	{Z30.D}, P0/Z, [X24, Z30.D,LSL #3]    [2]

0x41ba90 MOVPRFX	Z11, Z30

0x41ba94 FABS	Z11.D, P0/M, Z30.D

0x41ba98 SXTW	Z31.D, P0/M, Z31.D

0x41ba9c SXTW	Z8.D, P0/M, Z8.D

0x41baa0 SXTW	Z28.D, P0/M, Z28.D

0x41baa4 SMIN	Z31.D, P0/M, Z31.D, Z22.D

0x41baa8 FCMGT	P1.D, P0/Z, Z30.D, #0

0x41baac SEL	Z28.D, P1, Z28.D, Z31.D

0x41bab0 SEL	Z31.D, P1, Z8.D, Z31.D

0x41bab4 SEL	Z9.D, P1, Z27.D, Z8.D

0x41bab8 SEL	Z8.D, P1, Z8.D, Z27.D

0x41babc MOVPRFX	Z10, Z26

0x41bac0 MLA	Z10.D, P0/M, Z8.D, Z7.D

0x41bac4 LD1D	{Z12.D}, P0/Z, [X26, Z10.D,LSL #3]    [7]

0x41bac8 LD1D	{Z29.D}, P0/Z, [X27, Z29.D,SXTW #3]    [9]

0x41bacc MOVPRFX	Z13, Z26

0x41bad0 MLA	Z13.D, P0/M, Z16.D, Z28.D

0x41bad4 LD1D	{Z31.D}, P0/Z, [X27, Z31.D,LSL #3]    [10]

0x41bad8 FDIV	Z11.D, P0/M, Z11.D, Z12.D

0x41badc MAD	Z28.D, P0/M, Z18.D, Z26.D

0x41bae0 FMAD	Z29.D, P0/M, Z11.D, Z29.D

0x41bae4 FSUB	Z14.D, Z23.D, Z11.D

0x41bae8 MOVPRFX	Z23, Z26

0x41baec MLA	Z23.D, P0/M, Z9.D, Z16.D

0x41baf0 FDIV	Z29.D, P0/M, Z29.D, Z31.D

0x41baf4 MOVPRFX	Z31, Z26

0x41baf8 MLA	Z31.D, P0/M, Z8.D, Z16.D

0x41bafc LD1D	{Z12.D}, P0/Z, [X19, Z31.D,LSL #3]    [1]

0x41bb00 LD1D	{Z13.D}, P0/Z, [X19, Z13.D,LSL #3]    [3]

0x41bb04 LD1D	{Z23.D}, P0/Z, [X19, Z23.D,LSL #3]    [4]

0x41bb08 FSUB	Z24.D, Z23.D, Z12.D

0x41bb0c FSUB	Z15.D, Z12.D, Z13.D

0x41bb10 FABD	Z23.D, P0/M, Z23.D, Z12.D

0x41bb14 FCMGT	P1.D, P0/Z, Z24.D, #0

0x41bb18 FMUL	Z15.D, Z24.D, Z15.D

0x41bb1c MOVPRFX	Z24, Z11

0x41bb20 FSUBR	Z24.D, P0/M, Z24.D, #1

0x41bb24 MOVPRFX	Z11, Z24

0x41bb28 FNEG	Z11.D, P0/M, Z24.D

0x41bb2c SEL	Z24.D, P1, Z24.D, Z11.D

0x41bb30 MOVPRFX	Z11, Z12

0x41bb34 FABD	Z11.D, P0/M, Z11.D, Z13.D

0x41bb38 MOVPRFX	Z13, Z11

0x41bb3c FMINNM	Z13.D, P0/M, Z13.D, Z23.D

0x41bb40 FCMGT	P2.D, P0/Z, Z15.D, #0

0x41bb44 FMUL	Z11.D, Z11.D, Z29.D

0x41bb48 FMAD	Z23.D, P0/M, Z14.D, Z11.D

0x41bb4c FMUL	Z23.D, Z23.D, Z25.D

0x41bb50 FMINNM	Z23.D, P0/M, Z23.D, Z13.D

0x41bb54 FMUL	Z23.D, Z23.D, Z24.D

0x41bb58 DUP	Z24.D, #0

0x41bb5c SEL	Z23.D, P2, Z23.D, Z24.D

0x41bb60 MOVPRFX	Z24, Z26

0x41bb64 MLA	Z24.D, P0/M, Z17.D, Z27.D

0x41bb68 FADD	Z23.D, Z23.D, Z12.D

0x41bb6c FMUL	Z23.D, Z23.D, Z30.D

0x41bb70 ST1D	{Z23.D}, P0, [X25, Z24.D,LSL #3]    [11]

0x41bb74 MOVPRFX	Z24, Z26

0x41bb78 MLA	Z24.D, P0/M, Z8.D, Z18.D

0x41bb7c MOVPRFX	Z8, Z26

0x41bb80 MLA	Z8.D, P0/M, Z9.D, Z18.D

0x41bb84 LD1D	{Z24.D}, P0/Z, [X21, Z24.D,LSL #3]    [5]

0x41bb88 LD1D	{Z28.D}, P0/Z, [X21, Z28.D,LSL #3]    [6]

0x41bb8c LD1D	{Z8.D}, P0/Z, [X21, Z8.D,LSL #3]    [8]

0x41bb90 LD1D	{Z31.D}, P0/Z, [X19, Z31.D,LSL #3]    [1]

0x41bb94 LD1D	{Z9.D}, P0/Z, [X26, Z10.D,LSL #3]    [7]

0x41bb98 FMUL	Z31.D, Z9.D, Z31.D

0x41bb9c MOVPRFX	Z9, Z23

0x41bba0 FABS	Z9.D, P0/M, Z23.D

0x41bba4 FSUB	Z30.D, Z24.D, Z28.D

0x41bba8 FABD	Z28.D, P0/M, Z28.D, Z24.D

0x41bbac FMUL	Z29.D, Z28.D, Z29.D

0x41bbb0 FDIVR	Z31.D, P0/M, Z31.D, Z9.D

0x41bbb4 FSUB	Z9.D, Z8.D, Z24.D

0x41bbb8 FABD	Z8.D, P0/M, Z8.D, Z24.D

0x41bbbc FMLA	Z29.D, P0/M, Z8.D, Z14.D

0x41bbc0 FCMGT	P1.D, P0/Z, Z9.D, #0

0x41bbc4 FMINNM	Z28.D, P0/M, Z28.D, Z8.D

0x41bbc8 FMUL	Z30.D, Z9.D, Z30.D

0x41bbcc FMUL	Z29.D, Z29.D, Z25.D

0x41bbd0 FMINNM	Z28.D, P0/M, Z28.D, Z29.D

0x41bbd4 FSUBR	Z31.D, P0/M, Z31.D, #1

0x41bbd8 MOVPRFX	Z9, Z31

0x41bbdc FNEG	Z9.D, P0/M, Z31.D

0x41bbe0 SEL	Z31.D, P1, Z31.D, Z9.D

0x41bbe4 FCMLE	P1.D, P0/Z, Z30.D, #0

0x41bbe8 FMUL	Z28.D, Z31.D, Z28.D

0x41bbec CPY	Z28.D, P1/M, #0

0x41bbf0 FADD	Z24.D, Z28.D, Z24.D

0x41bbf4 FMUL	Z23.D, Z24.D, Z23.D

0x41bbf8 MOVPRFX	Z24, Z26

0x41bbfc MLA	Z24.D, P0/M, Z19.D, Z27.D

0x41bc00 ST1D	{Z23.D}, P0, [X22, Z24.D,LSL #3]    [12]

0x41bc04 B.NE	41ba48

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 158 - 202

--------------------------------------------------------------------------------

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.43
Bottlenecks	P6, P7,
Function	.omp_outlined..12
Source	context.h:69-69,advec_cell.cpp:158-202
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	46.55
Front-end cycles	14.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	48.00
P6 cycles	48.00
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.42
Nb FLOP add-sub	36.00
Nb FLOP mul	44.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.33
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.28
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	96.15
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	57.69
Vector-efficiency ratio all	96.71
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	97.12
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	94.41

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.43
Bottlenecks	P6, P7,
Function	.omp_outlined..12
Source	context.h:69-69,advec_cell.cpp:158-202
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	46.55
Front-end cycles	14.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	48.00
P6 cycles	48.00
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.42
Nb FLOP add-sub	36.00
Nb FLOP mul	44.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.33
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.28
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	96.15
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	57.69
Vector-efficiency ratio all	96.71
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	97.12
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	94.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..12
Source file and lines	advec_cell.cpp:158-202
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:158-202

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 96% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 48.00 to 46.55 cycles (1.03x speedup).

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU addition or subtraction instructions are used in vector version.
57% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (12 inside FMA instructions)
56: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 384 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	48.00	48.00	1.00	1.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	48.00	48.00	11.50	11.50	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.00
Data deps.	1.00
Overall L1	48.00

Vectorization ratios

INT

all	67%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	94%
fma	100%
other	40%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	79%
load	100%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	57%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ba48

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z28.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z26.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z26.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z29.D, Z3.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z27, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z27.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z31.D, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z8.D, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z5.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z11, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z11.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z8.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SMIN Z31.D, P0/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z28.D, P1, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z9.D, P1, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z8.D, P1, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z8.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X27, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z13, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z13.D, P0/M, Z16.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X27, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z11.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MAD Z28.D, P0/M, Z18.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMAD Z29.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z14.D, Z23.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z9.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z8.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X19, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X19, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z24.D, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z15.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z24.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z15.D, Z24.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z24, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z24.D, P0/M, Z24.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z11.D, P0/M, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z24.D, P1, Z24.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z11.D, P0/M, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z13, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z13.D, P0/M, Z13.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P2.D, P0/Z, Z15.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z11.D, Z11.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z23.D, P0/M, Z14.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z23.D, P0/M, Z23.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DUP Z24.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z17.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z23.D, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X25, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z8.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z8, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z9.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z24.D}, P0/Z, [X21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X21, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z8.D}, P0/Z, [X21, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X19, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z9.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z28.D, P0/M, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z31.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z9.D, Z8.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z8.D, P0/M, Z8.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z8.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P1.D, P0/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z28.D, P0/M, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z28.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z31.D, P0/M, Z31.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z9.D, P0/M, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLE P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z28.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
CPY Z28.D, P1/M, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z19.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41ba48 <.omp_outlined..12+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..12
Source file and lines	advec_cell.cpp:158-202
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:158-202

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU addition or subtraction instructions are used in vector version.
57% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (12 inside FMA instructions)
56: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 384 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	48.00	48.00	1.00	1.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	48.00	48.00	11.50	11.50	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.00
Data deps.	1.00
Overall L1	48.00

Vectorization ratios

INT

all	67%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	94%
fma	100%
other	40%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	79%
load	100%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	57%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ba48

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z28.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z26.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z26.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z29.D, Z3.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z27, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z27.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z31.D, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z8.D, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z5.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z11, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z11.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z8.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SMIN Z31.D, P0/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z28.D, P1, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z9.D, P1, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z8.D, P1, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z8.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X27, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z13, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z13.D, P0/M, Z16.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X27, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z11.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MAD Z28.D, P0/M, Z18.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMAD Z29.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z14.D, Z23.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z9.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z8.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X19, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X19, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z24.D, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z15.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z24.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z15.D, Z24.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z24, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z24.D, P0/M, Z24.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z11.D, P0/M, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z24.D, P1, Z24.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z11.D, P0/M, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z13, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z13.D, P0/M, Z13.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P2.D, P0/Z, Z15.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z11.D, Z11.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z23.D, P0/M, Z14.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z23.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z23.D, P0/M, Z23.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DUP Z24.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z17.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z23.D, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X25, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z8.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z8, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z9.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z24.D}, P0/Z, [X21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X21, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z8.D}, P0/Z, [X21, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X19, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z9.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z28.D, P0/M, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z31.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z9.D, Z8.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z8.D, P0/M, Z8.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z8.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P1.D, P0/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z28.D, P0/M, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z28.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z31.D, P0/M, Z31.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z9.D, P0/M, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLE P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z28.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
CPY Z28.D, P1/M, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z19.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41ba48 <.omp_outlined..12+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code