OV - exec - Loop 273

0x4240ec LDR	D16, [X20]    [3]

0x4240f0 LDR	D17, [X19]    [7]

0x4240f4 MOVPRFX	Z6, Z0

0x4240f8 SDIV	Z6.D, P0/M, Z6.D, Z2.D

0x4240fc MOVPRFX	Z7, Z0

0x424100 MLS	Z7.D, P0/M, Z6.D, Z2.D

0x424104 MOVPRFX	Z18, Z6

0x424108 SXTW	Z18.D, P0/M, Z6.D

0x42410c ADD	Z0.D, Z0.D, Z1.D

0x424110 SUBS	X1, X1, X18

0x424114 FMUL	D16, D17, D16

0x424118 MOVPRFX	Z17, Z7

0x42411c SXTW	Z17.D, P0/M, Z7.D

0x424120 MOVPRFX	Z19, Z17

0x424124 MLA	Z19.D, P0/M, Z18.D, Z3.D

0x424128 DUP	Z16.D, Z16.D[0]

0x42412c ST1D	{Z16.D}, P0, [X8, Z19.D,LSL #3]    [5]

0x424130 MOVPRFX	Z16, Z17

0x424134 MLA	Z16.D, P0/M, Z18.D, Z4.D

0x424138 LD1D	{Z6.D}, P0/Z, [X10, Z6.D,SXTW #3]    [4]

0x42413c ST1D	{Z6.D}, P0, [X11, Z16.D,LSL #3]    [1]

0x424140 LD1D	{Z6.D}, P0/Z, [X13, Z7.D,SXTW #3]    [2]

0x424144 MOVPRFX	Z7, Z17

0x424148 MLA	Z7.D, P0/M, Z18.D, Z5.D

0x42414c ST1D	{Z6.D}, P0, [X14, Z7.D,LSL #3]    [6]

0x424150 B.NE	4240ec

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp: 78 - 82

--------------------------------------------------------------------------------

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.46
Bottlenecks	P6, P7,
Function	.omp_outlined..8#0x423ff0
Source	context.h:69-69,initialise_chunk.cpp:78-82
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	3.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.13
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	58.33
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	83.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	30.00
Vector-efficiency ratio all	90.63
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.46
Bottlenecks	P6, P7,
Function	.omp_outlined..8#0x423ff0
Source	context.h:69-69,initialise_chunk.cpp:78-82
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	3.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.13
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	58.33
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	83.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	30.00
Vector-efficiency ratio all	90.63
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..8#0x423ff0
Source file and lines	initialise_chunk.cpp:78-82
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp:78-82

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 90% of vector register length is used (average across all VPU instructions).

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
83% of VPU addition or subtraction instructions are used in vector version.
30% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 80 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	8.00	8.00	2.00	2.00	2.50	2.50	2.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	8.00	8.00	2.00	2.00	2.50	2.50	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.25
Data deps.	2.00
Overall L1	8.00

Vectorization ratios

all	58%
load	50%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

10% of peak load performance is reached (10.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4240ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVPRFX Z6, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z6.D, P0/M, Z6.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z7, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z7.D, P0/M, Z6.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MOVPRFX Z18, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z18.D, P0/M, Z6.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUBS X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMUL D16, D17, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
MOVPRFX Z17, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z17.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z19.D, P0/M, Z18.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
DUP Z16.D, Z16.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ST1D {Z16.D}, P0, [X8, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
MOVPRFX Z16, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z16.D, P0/M, Z18.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z6.D}, P0/Z, [X10, Z6.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ST1D {Z6.D}, P0, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1D {Z6.D}, P0/Z, [X13, Z7.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z7, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z7.D, P0/M, Z18.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z6.D}, P0, [X14, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 4240ec <.omp_outlined..8+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..8#0x423ff0
Source file and lines	initialise_chunk.cpp:78-82
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp:78-82

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 90% of vector register length is used (average across all VPU instructions).

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
83% of VPU addition or subtraction instructions are used in vector version.
30% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 80 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	8.00	8.00	2.00	2.00	2.50	2.50	2.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	8.00	8.00	2.00	2.00	2.50	2.50	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.25
Data deps.	2.00
Overall L1	8.00

Vectorization ratios

all	58%
load	50%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

10% of peak load performance is reached (10.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4240ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVPRFX Z6, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z6.D, P0/M, Z6.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z7, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z7.D, P0/M, Z6.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MOVPRFX Z18, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z18.D, P0/M, Z6.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUBS X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMUL D16, D17, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
MOVPRFX Z17, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z17.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z19.D, P0/M, Z18.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
DUP Z16.D, Z16.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ST1D {Z16.D}, P0, [X8, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
MOVPRFX Z16, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z16.D, P0/M, Z18.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z6.D}, P0/Z, [X10, Z6.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ST1D {Z6.D}, P0, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1D {Z6.D}, P0/Z, [X13, Z7.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z7, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z7.D, P0/M, Z18.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z6.D}, P0, [X14, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 4240ec <.omp_outlined..8+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code