OV - exec - Loop 262

	Loop Id: 262	Module: exec	Source: advec_cell.cpp:118-125 [...]	Coverage: 2.46%

0x41b120 MOVPRFX	Z20, Z0

0x41b124 SDIV	Z20.D, P0/M, Z20.D, Z2.D

0x41b128 MOVPRFX	Z21, Z0

0x41b12c MLS	Z21.D, P0/M, Z20.D, Z2.D

0x41b130 ADD	Z20.D, Z3.D, Z20.D

0x41b134 ADD	Z22.D, Z4.D, Z21.D

0x41b138 MOVPRFX	Z23, Z22

0x41b13c SXTW	Z23.D, P0/M, Z22.D

0x41b140 SUBS	X12, X12, X10

0x41b144 ADD	Z21.D, Z19.D, Z21.D

0x41b148 ADD	Z0.D, Z0.D, Z1.D

0x41b14c SXTW	Z20.D, P0/M, Z20.D

0x41b150 MOVPRFX	Z24, Z23

0x41b154 MLA	Z24.D, P0/M, Z5.D, Z20.D

0x41b158 LD1D	{Z25.D}, P0/Z, [X23, Z24.D,LSL #3]    [12]

0x41b15c MOVPRFX	Z26, Z23

0x41b160 MLA	Z26.D, P0/M, Z6.D, Z20.D

0x41b164 LD1D	{Z26.D}, P0/Z, [X25, Z26.D,LSL #3]    [5]

0x41b168 MOVPRFX	Z27, Z7

0x41b16c MUL	Z27.D, P0/M, Z27.D, Z20.D

0x41b170 ADR	Z28.D, [Z27, Z22.D,SXTW]    [14]

0x41b174 MOVPRFX	Z30, Z17

0x41b178 MUL	Z30.D, P0/M, Z30.D, Z20.D

0x41b17c LD1D	{Z28.D}, P0/Z, [X27, Z28.D,LSL #3]    [4]

0x41b180 ADR	Z27.D, [Z27, Z21.D,SXTW]    [8]

0x41b184 MLA	Z23.D, P0/M, Z16.D, Z20.D

0x41b188 LD1D	{Z27.D}, P0/Z, [X27, Z27.D,LSL #3]    [13]

0x41b18c ADR	Z31.D, [Z30, Z22.D,SXTW]    [1]

0x41b190 LD1D	{Z29.D}, P0/Z, [X19, Z23.D,LSL #3]    [11]

0x41b194 FMUL	Z25.D, Z26.D, Z25.D

0x41b198 FADD	Z28.D, Z25.D, Z28.D

0x41b19c MUL	Z20.D, P0/M, Z20.D, Z18.D

0x41b1a0 ADR	Z22.D, [Z20, Z22.D,SXTW]    [6]

0x41b1a4 ADR	Z20.D, [Z20, Z21.D,SXTW]    [2]

0x41b1a8 FSUB	Z27.D, Z28.D, Z27.D

0x41b1ac LD1D	{Z28.D}, P0/Z, [X24, Z31.D,LSL #3]    [7]

0x41b1b0 FMAD	Z25.D, P0/M, Z29.D, Z28.D

0x41b1b4 ADR	Z28.D, [Z30, Z21.D,SXTW]    [9]

0x41b1b8 LD1D	{Z28.D}, P0/Z, [X24, Z28.D,LSL #3]    [10]

0x41b1bc LD1D	{Z22.D}, P0/Z, [X22, Z22.D,LSL #3]    [15]

0x41b1c0 LD1D	{Z20.D}, P0/Z, [X22, Z20.D,LSL #3]    [3]

0x41b1c4 FADD	Z22.D, Z22.D, Z26.D

0x41b1c8 FSUB	Z25.D, Z25.D, Z28.D

0x41b1cc FSUB	Z20.D, Z22.D, Z20.D

0x41b1d0 FDIV	Z25.D, P0/M, Z25.D, Z27.D

0x41b1d4 FDIVR	Z20.D, P0/M, Z20.D, Z27.D

0x41b1d8 ST1D	{Z20.D}, P0, [X23, Z24.D,LSL #3]    [12]

0x41b1dc ST1D	{Z25.D}, P0, [X19, Z23.D,LSL #3]    [11]

0x41b1e0 B.NE	41b120

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 118 - 125

--------------------------------------------------------------------------------

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.94
Bottlenecks	P6, P7,
Function	.omp_outlined..6
Source	context.h:69-69,advec_cell.cpp:118-125
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	15.75
Front-end cycles	6.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	18.00
P6 cycles	18.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.22
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.56
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.83
Vectorization ratio load	60.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	65.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.22
Vector-efficiency ratio all	89.06
Vector-efficiency ratio load	70.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	73.75
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.94
Bottlenecks	P6, P7,
Function	.omp_outlined..6
Source	context.h:69-69,advec_cell.cpp:118-125
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	15.75
Front-end cycles	6.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	18.00
P6 cycles	18.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.22
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.56
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.83
Vectorization ratio load	60.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	65.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.22
Vector-efficiency ratio all	89.06
Vector-efficiency ratio load	70.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	73.75
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..6
Source file and lines	advec_cell.cpp:118-125
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:118-125

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 89% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.00 to 15.75 cycles (1.14x speedup).

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
65% of VPU addition or subtraction instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	18.00	18.00	1.00	1.00	5.50	5.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	18.00	18.00	3.50	3.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.13
Data deps.	2.00
Overall L1	18.00

Vectorization ratios

INT

all	64%
load	60%
store	100%
mul	100%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	60%
store	100%
mul	100%
add-sub	65%
fma	100%
div/sqrt	100%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z21.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z3.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.D, Z4.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z23.D, P0/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z21.D, Z19.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z5.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z25.D}, P0/Z, [X23, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z26, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z26.D, P0/M, Z6.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z26.D}, P0/Z, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z27, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z27.D, P0/M, Z27.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z28.D, [Z27, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z27.D, [Z27, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z16.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X27, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z31.D, [Z30, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z20.D, P0/M, Z20.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z22.D, [Z20, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z20.D, [Z20, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z25.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADR Z28.D, [Z30, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X24, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X22, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X22, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z22.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z25.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z20.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z25.D, P0/M, Z25.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z20.D, P0/M, Z20.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z20.D}, P0, [X23, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z25.D}, P0, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41b120 <.omp_outlined..6+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..6
Source file and lines	advec_cell.cpp:118-125
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:118-125

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
65% of VPU addition or subtraction instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	18.00	18.00	1.00	1.00	5.50	5.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	18.00	18.00	3.50	3.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.13
Data deps.	2.00
Overall L1	18.00

Vectorization ratios

INT

all	64%
load	60%
store	100%
mul	100%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	60%
store	100%
mul	100%
add-sub	65%
fma	100%
div/sqrt	100%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z21.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z3.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.D, Z4.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z23.D, P0/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z21.D, Z19.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z5.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z25.D}, P0/Z, [X23, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z26, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z26.D, P0/M, Z6.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z26.D}, P0/Z, [X25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z27, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z27.D, P0/M, Z27.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z28.D, [Z27, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z27.D, [Z27, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z16.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X27, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z31.D, [Z30, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z20.D, P0/M, Z20.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z22.D, [Z20, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z20.D, [Z20, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z25.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADR Z28.D, [Z30, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X24, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X22, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X22, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z22.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z25.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z20.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z25.D, P0/M, Z25.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z20.D, P0/M, Z20.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z20.D}, P0, [X23, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z25.D}, P0, [X19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41b120 <.omp_outlined..6+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code