OV - exec - Loop 258

0x41f188 MOVPRFX	Z7, Z0

0x41f18c SDIV	Z7.D, P0/M, Z7.D, Z2.D

0x41f190 MOVPRFX	Z16, Z0

0x41f194 MLS	Z16.D, P0/M, Z7.D, Z2.D

0x41f198 SXTW	Z16.D, P0/M, Z16.D

0x41f19c ADD	Z0.D, Z0.D, Z1.D

0x41f1a0 SUBS	X0, X0, X16

0x41f1a4 SXTW	Z7.D, P0/M, Z7.D

0x41f1a8 MOVPRFX	Z17, Z16

0x41f1ac MLA	Z17.D, P0/M, Z7.D, Z3.D

0x41f1b0 ST1D	{Z5.D}, P0, [X10, Z17.D,LSL #3]    [2]

0x41f1b4 MOVPRFX	Z17, Z16

0x41f1b8 MLA	Z17.D, P0/M, Z7.D, Z4.D

0x41f1bc ST1D	{Z5.D}, P0, [X9, Z17.D,LSL #3]    [3]

0x41f1c0 MAD	Z7.D, P0/M, Z6.D, Z16.D

0x41f1c4 ST1D	{Z5.D}, P0, [X12, Z7.D,LSL #3]    [1]

0x41f1c8 B.NE	41f188

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp: 144 - 148

--------------------------------------------------------------------------------

144:     for (int j = (0); j < (yrange + 1); j++) {

145:       for (int i = (0); i < (xrange); i++) {

146:         field.vol_flux_y(i, j) = 0.0;

147:         field.mass_flux_y(i, j) = 0.0;

148:         field.yarea(i, j) = 0.0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.82
Bottlenecks	P6, P7,
Function	.omp_outlined..6#0x41f0a0
Source	context.h:69-69,build_field.cpp:144-148
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	2.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	68.75
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	95.31
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	85.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.82
Bottlenecks	P6, P7,
Function	.omp_outlined..6#0x41f0a0
Source	context.h:69-69,build_field.cpp:144-148
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	2.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	68.75
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	95.31
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	85.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..6#0x41f0a0
Source file and lines	build_field.cpp:144-148
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:144-148

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

80% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 96 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	6.00	6.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	6.00	6.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.13
Data deps.	2.00
Overall L1	6.00

Vectorization ratios

all	68%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f188

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z7, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z7.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z16, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z16.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X0, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z17, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z17.D, P0/M, Z7.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z5.D}, P0, [X10, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z17, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z17.D, P0/M, Z7.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z5.D}, P0, [X9, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z7.D, P0/M, Z6.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z5.D}, P0, [X12, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41f188 <.omp_outlined..6+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..6#0x41f0a0
Source file and lines	build_field.cpp:144-148
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:144-148

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

80% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 96 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	6.00	6.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	6.00	6.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.13
Data deps.	2.00
Overall L1	6.00

Vectorization ratios

all	68%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f188

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z7, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z7.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z16, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z16.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X0, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z17, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z17.D, P0/M, Z7.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z5.D}, P0, [X10, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z17, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z17.D, P0/M, Z7.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z5.D}, P0, [X9, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z7.D, P0/M, Z6.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z5.D}, P0, [X12, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41f188 <.omp_outlined..6+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code