OV - exec - Loop 241

	Loop Id: 241	Module: exec	Source: advec_cell.cpp:66-110 [...]	Coverage: 5.42%

0x41ac00 MOVPRFX	Z26, Z0

0x41ac04 SDIV	Z26.D, P0/M, Z26.D, Z2.D

0x41ac08 ADD	Z27.D, Z3.D, Z26.D

0x41ac0c MOVPRFX	Z28, Z0

0x41ac10 MLS	Z28.D, P0/M, Z26.D, Z2.D

0x41ac14 ADD	Z29.D, Z4.D, Z28.D

0x41ac18 MOVPRFX	Z26, Z29

0x41ac1c SXTW	Z26.D, P0/M, Z29.D

0x41ac20 SUBS	X13, X13, X11

0x41ac24 ADD	Z31.D, Z20.D, Z28.D

0x41ac28 ADD	Z8.D, Z6.D, Z28.D

0x41ac2c ADD	Z28.D, Z21.D, Z28.D

0x41ac30 ADD	Z0.D, Z0.D, Z1.D

0x41ac34 SXTW	Z27.D, P0/M, Z27.D

0x41ac38 MOVPRFX	Z30, Z26

0x41ac3c MLA	Z30.D, P0/M, Z5.D, Z27.D

0x41ac40 LD1D	{Z30.D}, P0/Z, [X23, Z30.D,LSL #3]    [6]

0x41ac44 MOVPRFX	Z10, Z30

0x41ac48 FABS	Z10.D, P0/M, Z30.D

0x41ac4c SXTW	Z31.D, P0/M, Z31.D

0x41ac50 SXTW	Z8.D, P0/M, Z8.D

0x41ac54 SXTW	Z28.D, P0/M, Z28.D

0x41ac58 SMIN	Z31.D, P0/M, Z31.D, Z22.D

0x41ac5c FCMGT	P1.D, P0/Z, Z30.D, #0

0x41ac60 SEL	Z28.D, P1, Z28.D, Z31.D

0x41ac64 SEL	Z31.D, P1, Z8.D, Z31.D

0x41ac68 SEL	Z9.D, P1, Z26.D, Z8.D

0x41ac6c SEL	Z8.D, P1, Z8.D, Z26.D

0x41ac70 MOVPRFX	Z11, Z8

0x41ac74 MLA	Z11.D, P0/M, Z7.D, Z27.D

0x41ac78 LD1D	{Z12.D}, P0/Z, [X25, Z11.D,LSL #3]    [11]

0x41ac7c LD1D	{Z29.D}, P0/Z, [X26, Z29.D,SXTW #3]    [1]

0x41ac80 LD1D	{Z31.D}, P0/Z, [X26, Z31.D,LSL #3]    [4]

0x41ac84 FDIV	Z10.D, P0/M, Z10.D, Z12.D

0x41ac88 FMAD	Z29.D, P0/M, Z10.D, Z29.D

0x41ac8c FDIV	Z29.D, P0/M, Z29.D, Z31.D

0x41ac90 MOVPRFX	Z31, Z16

0x41ac94 MUL	Z31.D, P0/M, Z31.D, Z27.D

0x41ac98 ADD	Z12.D, Z8.D, Z31.D

0x41ac9c ADD	Z14.D, Z31.D, Z28.D

0x41aca0 ADD	Z31.D, Z9.D, Z31.D

0x41aca4 LD1D	{Z13.D}, P0/Z, [X28, Z12.D,LSL #3]    [8]

0x41aca8 LD1D	{Z14.D}, P0/Z, [X28, Z14.D,LSL #3]    [5]

0x41acac LD1D	{Z31.D}, P0/Z, [X28, Z31.D,LSL #3]    [7]

0x41acb0 FSUB	Z23.D, Z31.D, Z13.D

0x41acb4 FSUB	Z15.D, Z13.D, Z14.D

0x41acb8 FABD	Z31.D, P0/M, Z31.D, Z13.D

0x41acbc FCMGT	P1.D, P0/Z, Z23.D, #0

0x41acc0 FMUL	Z15.D, Z23.D, Z15.D

0x41acc4 MOVPRFX	Z23, Z10

0x41acc8 FSUBR	Z23.D, P0/M, Z23.D, #1

0x41accc MOVPRFX	Z24, Z23

0x41acd0 FNEG	Z24.D, P0/M, Z23.D

0x41acd4 SEL	Z23.D, P1, Z23.D, Z24.D

0x41acd8 FDUP	Z24.D, #0

0x41acdc FCMGT	P1.D, P0/Z, Z15.D, #0

0x41ace0 FSUB	Z24.D, Z24.D, Z10.D

0x41ace4 MOVPRFX	Z10, Z13

0x41ace8 FABD	Z10.D, P0/M, Z10.D, Z14.D

0x41acec MOVPRFX	Z14, Z10

0x41acf0 FMINNM	Z14.D, P0/M, Z14.D, Z31.D

0x41acf4 FMUL	Z10.D, Z10.D, Z29.D

0x41acf8 FMAD	Z31.D, P0/M, Z24.D, Z10.D

0x41acfc FMUL	Z31.D, Z31.D, Z25.D

0x41ad00 FMINNM	Z31.D, P0/M, Z31.D, Z14.D

0x41ad04 FMUL	Z23.D, Z31.D, Z23.D

0x41ad08 DUP	Z31.D, #0

0x41ad0c SEL	Z23.D, P1, Z23.D, Z31.D

0x41ad10 FADD	Z23.D, Z23.D, Z13.D

0x41ad14 FMUL	Z23.D, Z23.D, Z30.D

0x41ad18 MOVPRFX	Z30, Z26

0x41ad1c MLA	Z30.D, P0/M, Z17.D, Z27.D

0x41ad20 ST1D	{Z23.D}, P0, [X22, Z30.D,LSL #3]    [12]

0x41ad24 MOVPRFX	Z30, Z18

0x41ad28 MUL	Z30.D, P0/M, Z30.D, Z27.D

0x41ad2c ADD	Z31.D, Z8.D, Z30.D

0x41ad30 ADD	Z28.D, Z30.D, Z28.D

0x41ad34 ADD	Z30.D, Z9.D, Z30.D

0x41ad38 LD1D	{Z31.D}, P0/Z, [X27, Z31.D,LSL #3]    [9]

0x41ad3c LD1D	{Z28.D}, P0/Z, [X27, Z28.D,LSL #3]    [2]

0x41ad40 LD1D	{Z30.D}, P0/Z, [X27, Z30.D,LSL #3]    [3]

0x41ad44 LD1D	{Z9.D}, P0/Z, [X28, Z12.D,LSL #3]    [8]

0x41ad48 LD1D	{Z10.D}, P0/Z, [X25, Z11.D,LSL #3]    [11]

0x41ad4c FMUL	Z9.D, Z10.D, Z9.D

0x41ad50 MOVPRFX	Z10, Z23

0x41ad54 FABS	Z10.D, P0/M, Z23.D

0x41ad58 FSUB	Z8.D, Z31.D, Z28.D

0x41ad5c FABD	Z28.D, P0/M, Z28.D, Z31.D

0x41ad60 FMUL	Z29.D, Z28.D, Z29.D

0x41ad64 FDIVR	Z9.D, P0/M, Z9.D, Z10.D

0x41ad68 FSUB	Z10.D, Z30.D, Z31.D

0x41ad6c FABD	Z30.D, P0/M, Z30.D, Z31.D

0x41ad70 FMAD	Z24.D, P0/M, Z30.D, Z29.D

0x41ad74 FCMGT	P1.D, P0/Z, Z10.D, #0

0x41ad78 FMINNM	Z28.D, P0/M, Z28.D, Z30.D

0x41ad7c FMUL	Z8.D, Z10.D, Z8.D

0x41ad80 FMUL	Z24.D, Z24.D, Z25.D

0x41ad84 FMINNM	Z24.D, P0/M, Z24.D, Z28.D

0x41ad88 FSUBR	Z9.D, P0/M, Z9.D, #1

0x41ad8c MOVPRFX	Z10, Z9

0x41ad90 FNEG	Z10.D, P0/M, Z9.D

0x41ad94 SEL	Z9.D, P1, Z9.D, Z10.D

0x41ad98 FCMLE	P1.D, P0/Z, Z8.D, #0

0x41ad9c FMUL	Z24.D, Z9.D, Z24.D

0x41ada0 CPY	Z24.D, P1/M, #0

0x41ada4 FADD	Z24.D, Z24.D, Z31.D

0x41ada8 FMUL	Z23.D, Z24.D, Z23.D

0x41adac MOVPRFX	Z24, Z26

0x41adb0 MLA	Z24.D, P0/M, Z19.D, Z27.D

0x41adb4 ST1D	{Z23.D}, P0, [X24, Z24.D,LSL #3]    [10]

0x41adb8 B.NE	41ac00

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 66 - 110

--------------------------------------------------------------------------------

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.42
Bottlenecks	P6, P7,
Function	.omp_outlined..4
Source	context.h:69-69,advec_cell.cpp:66-110
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	47.50
CQA cycles if no scalar integer	47.50
CQA cycles if FP arith vectorized	47.50
CQA cycles if fully vectorized	46.05
Front-end cycles	13.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	47.50
P6 cycles	47.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.44
Nb FLOP add-sub	36.00
Nb FLOP mul	44.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.43
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	81.82
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	96.30
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	61.22
Vector-efficiency ratio all	96.68
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	97.22
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	94.07

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.42
Bottlenecks	P6, P7,
Function	.omp_outlined..4
Source	context.h:69-69,advec_cell.cpp:66-110
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	47.50
CQA cycles if no scalar integer	47.50
CQA cycles if FP arith vectorized	47.50
CQA cycles if fully vectorized	46.05
Front-end cycles	13.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	47.50
P6 cycles	47.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.44
Nb FLOP add-sub	36.00
Nb FLOP mul	44.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.43
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	81.82
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	96.30
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	61.22
Vector-efficiency ratio all	96.68
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	97.22
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	94.07

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..4
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:66-110

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 96% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 47.50 to 46.05 cycles (1.03x speedup).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU addition or subtraction instructions are used in vector version.
61% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (12 inside FMA instructions)
56: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 384 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	47.50	47.50	1.00	1.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	47.50	47.50	11.50	11.50	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.88
Data deps.	1.00
Overall L1	47.50

Vectorization ratios

INT

all	71%
load	100%
store	100%
mul	100%
add-sub	94%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	61%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.50 cycles. At this rate:

8% of peak load performance is reached (8.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ac00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z26.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z27.D, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z28.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z31.D, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z8.D, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z5.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X23, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z10.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z8.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SMIN Z31.D, P0/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z28.D, P1, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z9.D, P1, Z26.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z8.D, P1, Z8.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z11.D, P0/M, Z7.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X26, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X26, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z10.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMAD Z29.D, P0/M, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z31, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z12.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z14.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P0/Z, [X28, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X28, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z23.D, Z31.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z15.D, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z31.D, P0/M, Z31.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z15.D, Z23.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z23, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z23.D, P0/M, Z23.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z24.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z15.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FSUB Z24.D, Z24.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z10.D, P0/M, Z10.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z14, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z14.D, P0/M, Z14.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z31.D, P0/M, Z24.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z31.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z31.D, P0/M, Z31.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z31.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DUP Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z23.D, Z23.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z17.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z23.D}, P0, [X22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z30, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z31.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z31.D}, P0/Z, [X27, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X27, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X28, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z9.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z10.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z28.D, P0/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z10.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z30.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z24.D, P0/M, Z30.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P1.D, P0/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z10.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z24.D, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z24.D, P0/M, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z9.D, P0/M, Z9.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z10.D, P0/M, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z9.D, P1, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLE P1.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z24.D, Z9.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
CPY Z24.D, P1/M, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z24.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z19.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z23.D}, P0, [X24, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41ac00 <.omp_outlined..4+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..4
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:66-110

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU addition or subtraction instructions are used in vector version.
61% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (12 inside FMA instructions)
56: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 384 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	47.50	47.50	1.00	1.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	47.50	47.50	11.50	11.50	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.88
Data deps.	1.00
Overall L1	47.50

Vectorization ratios

INT

all	71%
load	100%
store	100%
mul	100%
add-sub	94%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	61%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.50 cycles. At this rate:

8% of peak load performance is reached (8.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ac00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z26.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z27.D, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z28.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z31.D, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z8.D, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z5.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X23, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z10.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z8.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SMIN Z31.D, P0/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z28.D, P1, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.D, P1, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z9.D, P1, Z26.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z8.D, P1, Z8.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z11.D, P0/M, Z7.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X26, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X26, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z10.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMAD Z29.D, P0/M, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z31, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z12.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z14.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P0/Z, [X28, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X28, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z23.D, Z31.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z15.D, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z31.D, P0/M, Z31.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z15.D, Z23.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z23, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z23.D, P0/M, Z23.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z24.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z15.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FSUB Z24.D, Z24.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z10.D, P0/M, Z10.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z14, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z14.D, P0/M, Z14.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z31.D, P0/M, Z24.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z31.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z31.D, P0/M, Z31.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z31.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DUP Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z23.D, Z23.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z17.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z23.D}, P0, [X22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z30, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z31.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z31.D}, P0/Z, [X27, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X27, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X28, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z9.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z10.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z28.D, P0/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z10.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z30.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z24.D, P0/M, Z30.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P1.D, P0/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z10.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z24.D, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z24.D, P0/M, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z9.D, P0/M, Z9.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z10.D, P0/M, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z9.D, P1, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLE P1.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z24.D, Z9.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
CPY Z24.D, P1/M, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z24.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z24, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z19.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z23.D}, P0, [X24, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41ac00 <.omp_outlined..4+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code