OV - exec - Loop 238

	Loop Id: 238	Module: exec	Source: advec_mom.cpp:63-66 [...]	Coverage: 1.57%

0x41cb6c MOVPRFX	Z18, Z0

0x41cb70 SDIV	Z18.D, P0/M, Z18.D, Z2.D

0x41cb74 ADD	Z19.D, Z3.D, Z18.D

0x41cb78 MOVPRFX	Z20, Z0

0x41cb7c MLS	Z20.D, P0/M, Z18.D, Z2.D

0x41cb80 ADD	Z20.D, Z4.D, Z20.D

0x41cb84 SUBS	X12, X12, X10

0x41cb88 ADD	Z18.D, Z7.D, Z18.D

0x41cb8c ADD	Z0.D, Z0.D, Z1.D

0x41cb90 SXTW	Z20.D, P0/M, Z20.D

0x41cb94 SXTW	Z18.D, P0/M, Z18.D

0x41cb98 SXTW	Z19.D, P0/M, Z19.D

0x41cb9c MOVPRFX	Z21, Z20

0x41cba0 MLA	Z21.D, P0/M, Z5.D, Z19.D

0x41cba4 LD1D	{Z21.D}, P0/Z, [X24, Z21.D,LSL #3]    [5]

0x41cba8 MOVPRFX	Z22, Z20

0x41cbac MLA	Z22.D, P0/M, Z6.D, Z19.D

0x41cbb0 ST1D	{Z21.D}, P0, [X22, Z22.D,LSL #3]    [4]

0x41cbb4 MAD	Z18.D, P0/M, Z16.D, Z20.D

0x41cbb8 LD1D	{Z18.D}, P0/Z, [X28, Z18.D,LSL #3]    [2]

0x41cbbc FADD	Z18.D, Z18.D, Z21.D

0x41cbc0 MOVPRFX	Z21, Z20

0x41cbc4 MLA	Z21.D, P0/M, Z16.D, Z19.D

0x41cbc8 LD1D	{Z21.D}, P0/Z, [X28, Z21.D,LSL #3]    [1]

0x41cbcc MAD	Z19.D, P0/M, Z17.D, Z20.D

0x41cbd0 FSUB	Z18.D, Z18.D, Z21.D

0x41cbd4 ST1D	{Z18.D}, P0, [X26, Z19.D,LSL #3]    [3]

0x41cbd8 B.NE	41cb6c

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 63 - 66

--------------------------------------------------------------------------------

63:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

64:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks	P6, P7,
Function	.omp_outlined..4#0x41ca30
Source	context.h:69-69,advec_mom.cpp:63-66
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	10.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.50
CQA cycles if fully vectorized	10.50
Front-end cycles	3.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	10.50
P6 cycles	10.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.76
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.24
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	77.78
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	90.91
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	37.50
Vector-efficiency ratio all	97.22
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	93.18
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks	P6, P7,
Function	.omp_outlined..4#0x41ca30
Source	context.h:69-69,advec_mom.cpp:63-66
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	10.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.50
CQA cycles if fully vectorized	10.50
Front-end cycles	3.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	10.50
P6 cycles	10.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.76
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.24
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	77.78
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	90.91
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	37.50
Vector-efficiency ratio all	97.22
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	93.18
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..4#0x41ca30
Source file and lines	advec_mom.cpp:63-66
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:63-66

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

77% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU addition or subtraction instructions are used in vector version.
37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 96 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	10.50	10.50	1.00	1.00	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	10.50	10.50	1.00	1.00	2.50	2.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.50
Data deps.	2.00
Overall L1	10.50

Vectorization ratios

INT

all	76%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	100%
other	44%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	77%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
div/sqrt	100%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41cb6c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z20.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z21.D, P0/M, Z5.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z21.D}, P0/Z, [X24, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z22, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X22, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z18.D, P0/M, Z16.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z18.D}, P0/Z, [X28, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z21.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z21.D}, P0/Z, [X28, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z18.D}, P0, [X26, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41cb6c <.omp_outlined..4+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..4#0x41ca30
Source file and lines	advec_mom.cpp:63-66
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:63-66

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

77% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU addition or subtraction instructions are used in vector version.
37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 96 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	10.50	10.50	1.00	1.00	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	10.50	10.50	1.00	1.00	2.50	2.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.50
Data deps.	2.00
Overall L1	10.50

Vectorization ratios

INT

all	76%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	100%
other	44%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	77%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
div/sqrt	100%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41cb6c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z20.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z21.D, P0/M, Z5.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z21.D}, P0/Z, [X24, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z22, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z6.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X22, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z18.D, P0/M, Z16.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z18.D}, P0/Z, [X28, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z21.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z21.D}, P0/Z, [X28, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z18.D}, P0, [X26, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41cb6c <.omp_outlined..4+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code